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Paper Abstract and Keywords
Presentation 2010-11-12 15:30
Design Feasibility of Si Wire GAA MOSFET -- Analytical model for the design guideline --
Shunsuke Nakano, Yasuhisa Omura (Kansai Univ.) SDM2010-184
Abstract (in Japanese) (See Japanese page) 
(in English) This paper proposes a simple model to examine the design feasibility of Si wire gate-all-around (GAA) metal-oxide-semiconductor field-effect transistor (MOSFET) having a sub-30-nm channel. Although the model has one fitting parameter, it successfully reproduces the past simulation results. The practical value of the fitting parameter is examined with the physical consideration, and the availability of the proposed model is revealed.
Keyword (in Japanese) (See Japanese page) 
(in English) GAA MOSFET / scaling / minimal channel modeling / charge-sharing model / tunnel current / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 274, SDM2010-184, pp. 71-76, Nov. 2010.
Paper # SDM2010-184 
Date of Issue 2010-11-04 (SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2010-184

Conference Information
Committee SDM  
Conference Date 2010-11-11 - 2010-11-12 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Process, Device, Circuit Simulations, etc 
Paper Information
Registration To SDM 
Conference Code 2010-11-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design Feasibility of Si Wire GAA MOSFET 
Sub Title (in English) Analytical model for the design guideline 
Keyword(1) GAA MOSFET  
Keyword(2) scaling  
Keyword(3) minimal channel modeling  
Keyword(4) charge-sharing model  
Keyword(5) tunnel current  
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1st Author's Name Shunsuke Nakano  
1st Author's Affiliation Kansai University (Kansai Univ.)
2nd Author's Name Yasuhisa Omura  
2nd Author's Affiliation Kansai University (Kansai Univ.)
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Speaker Author-1 
Date Time 2010-11-12 15:30:00 
Presentation Time 25 minutes 
Registration for SDM 
Paper # SDM2010-184 
Volume (vol) vol.110 
Number (no) no.274 
Page pp.71-76 
#Pages 6 
Date of Issue 2010-11-04 (SDM) 

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