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| Presentation | 2010-11-30 14:15 An FPGA Implementation of CRC Slicing-by-N algorithms Amila Akagic, Hideharu Amano (Keio Univ.)  RECONF2010-42 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Cyclic Redundancy Check (CRC) is an error detection scheme that detects corruption of digital content during data transmission, processing or storage. The process of calculating the CRC values of a large amounts of data is most computationally intensive process when processing a protocol. The proposed software solutions are not able to generate CRC values at a very high speed (10 Gbps or higher), due to the limitations of current speed of processors. This paper examines new computer architectures for accelerating the process of calculating CRC using programmable logic - FPGA. Our hardware implementation was based on a newly proposed "Slicing-by-N" CRC algorithms that are using multiple tables and reading 32, 64, 128 and 256 bits at a time. We examine achievable clock speed, throughput and area utilization. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Cyclic Redundancy Check (CRC) / FPGA / VHDL / network processing / field programmable / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 319, RECONF2010-42, pp. 19-24, Nov. 2010. | |
| Paper # | RECONF2010-42 | |
| Date of Issue | 2010-11-23 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2010-42 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2010-11-29 - 2010-12-01 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kyushu University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2010 ―New Field of VLSI Design― |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2010-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An FPGA Implementation of CRC Slicing-by-N algorithms |
| Sub Title (in English) | |
| Keyword(1) | Cyclic Redundancy Check (CRC) |
| Keyword(2) | FPGA |
| Keyword(3) | VHDL |
| Keyword(4) | network processing |
| Keyword(5) | field programmable |
| Keyword(6) | |
| Keyword(7) | |
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| 1st Author's Name | Amila Akagic |
| 1st Author's Affiliation | Keio University (Keio Univ.) |
| 2nd Author's Name | Hideharu Amano |
| 2nd Author's Affiliation | Keio University (Keio Univ.) |
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| Speaker | Author-1 |
| Date Time | 2010-11-30 14:15:00 |
| Presentation Time | 20 minutes |
| Registration for | RECONF |
| Paper # | RECONF2010-42 |
| Volume (vol) | vol.110 |
| Number (no) | no.319 |
| Page | pp.19-24 |
| #Pages | 6 |
| Date of Issue | 2010-11-23 (RECONF) |
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