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Paper Abstract and Keywords
Presentation 2010-11-30 11:05
Evaluation of FPGA Implementation Techniques for High-Performance SoC Prototypes
Hideo Tanida (Univ. of Tokyo), Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST) VLD2010-68 DC2010-35
Abstract (in Japanese) (See Japanese page) 
(in English) With the increasing scale and shrinking time-to-market of SoC systems, prototype implementations of SoCs on FPGAs are commonly performed during development cycles. Also, efficient interconnect technologies such as Network-on-Chip (NoC) are expected to be called for in future SoC systems. Therefore, in this paper, we perform a study of interconnect technologies applicable to FPGA-based implementations of high-performance SoC prototypes, which is followed by evaluations of them. We have chosen CoreConnect PLB, Fast Simplex Link, AMBA AXI4-Stream as the evaluation targets. Measures used in the evaluation are transfer time, resource usage of the interconnects, power and energy consumed to complete operations.
Keyword (in Japanese) (See Japanese page) 
(in English) SoC / prototyping / FPGA / interconnect / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 316, VLD2010-68, pp. 79-84, Nov. 2010.
Paper # VLD2010-68 
Date of Issue 2010-11-22 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2010-11-29 - 2010-12-01 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyushu University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2010 ―New Field of VLSI Design― 
Paper Information
Registration To VLD 
Conference Code 2010-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Evaluation of FPGA Implementation Techniques for High-Performance SoC Prototypes 
Sub Title (in English)  
Keyword(1) SoC  
Keyword(2) prototyping  
Keyword(3) FPGA  
Keyword(4) interconnect  
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1st Author's Name Hideo Tanida  
1st Author's Affiliation The University of Tokyo (Univ. of Tokyo)
2nd Author's Name Hiroaki Yoshida  
2nd Author's Affiliation The University of Tokyo/CREST, Japan Science and Technology Agency (Univ. of Tokyo/JST)
3rd Author's Name Masahiro Fujita  
3rd Author's Affiliation The University of Tokyo/CREST, Japan Science and Technology Agency (Univ. of Tokyo/JST)
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Speaker Author-1 
Date Time 2010-11-30 11:05:00 
Presentation Time 20 minutes 
Registration for VLD 
Paper # VLD2010-68, DC2010-35 
Volume (vol) vol.110 
Number (no) no.316(VLD), no.317(DC) 
Page pp.79-84 
#Pages
Date of Issue 2010-11-22 (VLD, DC) 


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