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Paper Abstract and Keywords
Presentation 2010-12-01 11:25
A Sequential Test Generation Method and a Binding Method for Testability Using Behavioral Description
Ryoichi Inoue, Hiroaki Fujiwara, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (NAIST) VLD2010-76 DC2010-43
Abstract (in Japanese) (See Japanese page) 
(in English) Although many works on test generation algorithms for sequential circuits have been reported so far, it is still very hard to achieve high fault coverage because of the complexity of sequential test generation. Several test generation methods using behavioral description and functional register transfer level (RTL) circuits at high level have been proposed to accelerate test generation time. Among them, there are works on test generation methods for assignment decision diagrams (ADDs) that represent functional RTL circuits. However, the test sequence generated by those methods without considering resource binding cannot guarantee to achieve high fault coverage at gate level even if the test environment coverage at RTL is high. This paper proposes a test generation method that considers resource binding in order to achieve higher fault coverage than previous methods.
Keyword (in Japanese) (See Japanese page) 
(in English) Sequential test generation / behavioral synthesis / binding / test environment / assignment decision diagrams / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 317, DC2010-43, pp. 143-148, Nov. 2010.
Paper # DC2010-43 
Date of Issue 2010-11-22 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2010-76 DC2010-43

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2010-11-29 - 2010-12-01 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyushu University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2010 ―New Field of VLSI Design― 
Paper Information
Registration To DC 
Conference Code 2010-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Sequential Test Generation Method and a Binding Method for Testability Using Behavioral Description 
Sub Title (in English)  
Keyword(1) Sequential test generation  
Keyword(2) behavioral synthesis  
Keyword(3) binding  
Keyword(4) test environment  
Keyword(5) assignment decision diagrams  
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1st Author's Name Ryoichi Inoue  
1st Author's Affiliation Nihon University (Nihon Univ.)
2nd Author's Name Hiroaki Fujiwara  
2nd Author's Affiliation Nihon University (Nihon Univ.)
3rd Author's Name Toshinori Hosokawa  
3rd Author's Affiliation Nihon University (Nihon Univ.)
4th Author's Name Hideo Fujiwara  
4th Author's Affiliation Nara Institute of Science and Technology (NAIST)
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Speaker Author-1 
Date Time 2010-12-01 11:25:00 
Presentation Time 20 minutes 
Registration for DC 
Paper # VLD2010-76, DC2010-43 
Volume (vol) vol.110 
Number (no) no.316(VLD), no.317(DC) 
Page pp.143-148 
#Pages 6 
Date of Issue 2010-11-22 (VLD, DC) 

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