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| Presentation | 2010-12-01 10:10 Evaluation and Verification of Dependable Processor Architecture Using System-Level Fault-Injection Scheme Yohei Nakata (Kobe Univ.), Yasuhiro Ito, Yasuo Sugure, Shigeru Oho (Hitachi Ltd.), Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST)  VLD2010-74 DC2010-41 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We develop a fault case generator that can generate memory failures in aprocessor-in-the-loop simulation. The fault injection system (FIS) generates memory failure patterns based on a transistor-level simulation and SRAM failure model. By using this FIS, processors with 6T normal SRAM and with 7T/14T dependable SRAM can be evaluated and compared. We confirmed that the dependable SRAM reduces abnormal terminations and improves a system-level dependability in a vehicle engine control system. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Fault-Injection / SRAM / Dependable Processor / System-Level Verification / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 317, DC2010-41, pp. 125-130, Nov. 2010. | |
| Paper # | DC2010-41 | |
| Date of Issue | 2010-11-22 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2010-74 DC2010-41 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2010-11-29 - 2010-12-01 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kyushu University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2010 ―New Field of VLSI Design― |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2010-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation and Verification of Dependable Processor Architecture Using System-Level Fault-Injection Scheme |
| Sub Title (in English) | |
| Keyword(1) | Fault-Injection |
| Keyword(2) | SRAM |
| Keyword(3) | Dependable Processor |
| Keyword(4) | System-Level Verification |
| Keyword(5) | |
| Keyword(6) | |
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| Keyword(8) | |
| 1st Author's Name | Yohei Nakata |
| 1st Author's Affiliation | Kobe University (Kobe Univ.) |
| 2nd Author's Name | Yasuhiro Ito |
| 2nd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. (Hitachi Ltd.) |
| 3rd Author's Name | Yasuo Sugure |
| 3rd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. (Hitachi Ltd.) |
| 4th Author's Name | Shigeru Oho |
| 4th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. (Hitachi Ltd.) |
| 5th Author's Name | Hiroshi Kawaguchi |
| 5th Author's Affiliation | Kobe University (Kobe Univ.) |
| 6th Author's Name | Masahiko Yoshimoto |
| 6th Author's Affiliation | Kobe University/JST, CREST (Kobe Univ./JST) |
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| Speaker | Author-1 |
| Date Time | 2010-12-01 10:10:00 |
| Presentation Time | 20 minutes |
| Registration for | DC |
| Paper # | VLD2010-74, DC2010-41 |
| Volume (vol) | vol.110 |
| Number (no) | no.316(VLD), no.317(DC) |
| Page | pp.125-130 |
| #Pages | 6 |
| Date of Issue | 2010-11-22 (VLD, DC) |
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