Paper Abstract and Keywords |
Presentation |
2010-12-16 15:10
[Poster Presentation]
Evaluation of Power Gating Structures Focusing on Power Supply Noise with Measurement and Simulation Yasumichi Takai, Masanori Hashimoto, Takao Onoye (Osaka Univ.) ICD2010-109 Link to ES Tech. Rep. Archives: ICD2010-109 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper investigates the impact of power gating structure on power supply noise using 65nm test chip measurement and simulation. We focus on the body connection of power-gated circuits, and examine the contribution of a power-gated circuit as a decoupling capacitance during the sleep mode. Experimental results show that the well junction capacitance of the power-gated circuit with body-tied structure helps reduce power supply noise while a sharp drop cannot be mitigated due to its large RC time constant. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
on-chip power supply noise / power gating / well structure / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 110, no. 344, ICD2010-109, pp. 75-80, Dec. 2010. |
Paper # |
ICD2010-109 |
Date of Issue |
2010-12-09 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
ICD2010-109 Link to ES Tech. Rep. Archives: ICD2010-109 |
Conference Information |
Committee |
ICD |
Conference Date |
2010-12-16 - 2010-12-17 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
RCAST, Univ. of Tokyo |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Workshop for Graduate Student and Young Researchers |
Paper Information |
Registration To |
ICD |
Conference Code |
2010-12-ICD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Evaluation of Power Gating Structures Focusing on Power Supply Noise with Measurement and Simulation |
Sub Title (in English) |
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on-chip power supply noise |
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power gating |
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well structure |
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1st Author's Name |
Yasumichi Takai |
1st Author's Affiliation |
Osaka University (Osaka Univ.) |
2nd Author's Name |
Masanori Hashimoto |
2nd Author's Affiliation |
Osaka University (Osaka Univ.) |
3rd Author's Name |
Takao Onoye |
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Osaka University (Osaka Univ.) |
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Speaker |
Author-1 |
Date Time |
2010-12-16 15:10:00 |
Presentation Time |
120 minutes |
Registration for |
ICD |
Paper # |
ICD2010-109 |
Volume (vol) |
vol.110 |
Number (no) |
no.344 |
Page |
pp.75-80 |
#Pages |
6 |
Date of Issue |
2010-12-09 (ICD) |