Paper Abstract and Keywords |
Presentation |
2010-12-17 15:15
A Circuit Partitioning Strategy for 3-D Integrated Multipliers Kazuhito Sakai, Jubee Tada (Yamagata Univ.), Ryusuke Egawa, Hiroaki Kobayashi (Tohoku Univ.), Gensuke Goto (Yamagata Univ.) ICD2010-125 Link to ES Tech. Rep. Archives: ICD2010-125 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Three-dimensional(3-D) integration technologies attract a lot of attention to further enhance the performance of the LSI. To implement 3-D stacked arithmetic units, appropriate circuit partitioning strategies should be applied to exploit the potential of 3-D integration technologies. In this paper, we propose a circuit partitioning technology, which can improve the performance of arithmetic units with small overheads of vertical interconnects. To clarify the effectiveness of the proposed partitioning strategy, 3-D stacked parallel multipliers are designed and evaluated. The multipliers designed by the proposed circuit partitioning strategy achieve a 20% delay reduction compared to multipliers that is designed based on conventional 2-D implementations. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
3-D integration / multiplier / / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 110, no. 344, ICD2010-125, pp. 153-158, Dec. 2010. |
Paper # |
ICD2010-125 |
Date of Issue |
2010-12-09 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
ICD2010-125 Link to ES Tech. Rep. Archives: ICD2010-125 |
Conference Information |
Committee |
ICD |
Conference Date |
2010-12-16 - 2010-12-17 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
RCAST, Univ. of Tokyo |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Workshop for Graduate Student and Young Researchers |
Paper Information |
Registration To |
ICD |
Conference Code |
2010-12-ICD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Circuit Partitioning Strategy for 3-D Integrated Multipliers |
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3-D integration |
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multiplier |
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1st Author's Name |
Kazuhito Sakai |
1st Author's Affiliation |
Yamagata University (Yamagata Univ.) |
2nd Author's Name |
Jubee Tada |
2nd Author's Affiliation |
Yamagata University (Yamagata Univ.) |
3rd Author's Name |
Ryusuke Egawa |
3rd Author's Affiliation |
Tohoku University (Tohoku Univ.) |
4th Author's Name |
Hiroaki Kobayashi |
4th Author's Affiliation |
Tohoku University (Tohoku Univ.) |
5th Author's Name |
Gensuke Goto |
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Yamagata University (Yamagata Univ.) |
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Speaker |
Author-1 |
Date Time |
2010-12-17 15:15:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
ICD2010-125 |
Volume (vol) |
vol.110 |
Number (no) |
no.344 |
Page |
pp.153-158 |
#Pages |
6 |
Date of Issue |
2010-12-09 (ICD) |
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