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Paper Abstract and Keywords
Presentation 2011-02-14 11:25
Variation Aware Test Methodology Based on Statistical Static Timing Analysis
Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo (STARC) DC2010-62
Abstract (in Japanese) (See Japanese page) 
(in English) The continuing miniaturization of LSI dimension may cause parametric faults which exceed the specification due to process variations. Path delay testing is effective to test parametric faults, because parametric
faults affect path delay. In this paper, we propose an effective methodology for testing parametric faults. Proposed methodology divides the process area into two parts and extracts test-paths for each part. Then, path delay test patterns are generated for each of extracted test-path sets. In test phase, process parameters are measured from an on-chip sensor. According to the obtained process parameters, we select the test pattern to be used from two test patterns. Experimental results demonstrate our approach can reduce test cost while keeping the test quality.
Keyword (in Japanese) (See Japanese page) 
(in English) Statistical Static Timing Analysis / Parametric Faults / Path Delay Test / Adapvtive Test / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 413, DC2010-62, pp. 21-26, Feb. 2011.
Paper # DC2010-62 
Date of Issue 2011-02-07 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF DC2010-62

Conference Information
Committee DC  
Conference Date 2011-02-14 - 2011-02-14 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2011-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Variation Aware Test Methodology Based on Statistical Static Timing Analysis 
Sub Title (in English)  
Keyword(1) Statistical Static Timing Analysis  
Keyword(2) Parametric Faults  
Keyword(3) Path Delay Test  
Keyword(4) Adapvtive Test  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Michihiro Shintani  
1st Author's Affiliation Semiconductor Technology Academic Research Center (STARC)
2nd Author's Name Kazumi Hatayama  
2nd Author's Affiliation Semiconductor Technology Academic Research Center (STARC)
3rd Author's Name Takashi Aikyo  
3rd Author's Affiliation Semiconductor Technology Academic Research Center (STARC)
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Speaker Author-1 
Date Time 2011-02-14 11:25:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2010-62 
Volume (vol) vol.110 
Number (no) no.413 
Page pp.21-26 
#Pages 6 
Date of Issue 2011-02-07 (DC) 

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