IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2011-02-14 11:00
An Analysis of Critical Paths for Field Testing with Process Variation Consideration
Satoshi Kashiwazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushuu Univ) DC2010-61
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, it has the problem that good VLSIs in production testing become defective VLSIs in the fields because small delays on signal lines are caused by aged deterioration. Some field test methods have been proposed to detect defects caused by aged deterioration. However, it is difficult to detect small delay faults comprehensively in field testing from the view point of test application time. Therefore, it is important to select target paths in field testing. A target path is defined as a delay fault –propagation path pair. Some methods to select as long paths as possible using SDQM and calculate aging degrade at the pass. have been proposed as target path selection. However, these methods do not consider process variation caused when VLSIs are manufactured. In this paper, we evaluate the number of dangerous paths which are not critical at design phase but become critical after manufacturing VLSIs as a stage before proposing a path selection method for field testing. Experimental results for ISCAS’89 and ITC’99 benchmark circuits show that there are 20 dangerous paths for 1000 VLSIs in the maximum.
Keyword (in Japanese) (See Japanese page) 
(in English) process variation / field test / transition delay fault model / critical paths / small delay / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 413, DC2010-61, pp. 13-19, Feb. 2011.
Paper # DC2010-61 
Date of Issue 2011-02-07 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF DC2010-61

Conference Information
Committee DC  
Conference Date 2011-02-14 - 2011-02-14 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2011-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Analysis of Critical Paths for Field Testing with Process Variation Consideration 
Sub Title (in English)  
Keyword(1) process variation  
Keyword(2) field test  
Keyword(3) transition delay fault model  
Keyword(4) critical paths  
Keyword(5) small delay  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Satoshi Kashiwazaki  
1st Author's Affiliation Nihon University (Nihon Univ)
2nd Author's Name Toshinori Hosokawa  
2nd Author's Affiliation Nihon University (Nihon Univ)
3rd Author's Name Masayoshi Yoshimura  
3rd Author's Affiliation Kyuushuu University (Kyushuu Univ)
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2011-02-14 11:00:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2010-61 
Volume (vol) vol.110 
Number (no) no.413 
Page pp.13-19 
#Pages
Date of Issue 2011-02-07 (DC) 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan