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| Presentation | 2011-02-14 10:00 The development of the DDR3 memory module tester used on memory test processor Takeshi Asakawa, Satoshi Matsuno (Tokai Univ.), Hidekazu Tsuchiya (Hitachi), Tatsuya Seki, Shinichi Kmazawa (Techinica)  DC2010-59 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The testing for the memory module is necessary to warrant the quality in the memory module manufacturer. However, there are problems that the LSI tester is expensive and the low cost one can’t generate the arbitrary test patterns. Then, we developed a low-cost memory module tester with flexibility for the memory test and the evaluation. The memory test processor based on memory testing algorithm and the DDR3 memory module interface are implemented on FPGA in the tester. In this paper, we explain the architecture of the developed DDR memory module tester. In addition, we report on the evaluation result using the prototype. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | LSI testing / FPGA / DDR3 / memory module / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 413, DC2010-59, pp. 1-6, Feb. 2011. | |
| Paper # | DC2010-59 | |
| Date of Issue | 2011-02-07 (DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | DC2010-59 |
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| Conference Information | |
| Committee | DC |
| Conference Date | 2011-02-14 - 2011-02-14 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2011-02-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | The development of the DDR3 memory module tester used on memory test processor |
| Sub Title (in English) | |
| Keyword(1) | LSI testing |
| Keyword(2) | FPGA |
| Keyword(3) | DDR3 |
| Keyword(4) | memory module |
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| 1st Author's Name | Takeshi Asakawa |
| 1st Author's Affiliation | Tokai University (Tokai Univ.) |
| 2nd Author's Name | Satoshi Matsuno |
| 2nd Author's Affiliation | Tokai University (Tokai Univ.) |
| 3rd Author's Name | Hidekazu Tsuchiya |
| 3rd Author's Affiliation | Hitachi High-Tech Engineering Service Corporation (Hitachi) |
| 4th Author's Name | Tatsuya Seki |
| 4th Author's Affiliation | Techinica Co.Ltd (Techinica) |
| 5th Author's Name | Shinichi Kmazawa |
| 5th Author's Affiliation | Techinica Co.Ltd (Techinica) |
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| Speaker | Author-1 |
| Date Time | 2011-02-14 10:00:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | DC2010-59 |
| Volume (vol) | vol.110 |
| Number (no) | no.413 |
| Page | pp.1-6 |
| #Pages | 6 |
| Date of Issue | 2011-02-07 (DC) |
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