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Paper Abstract and Keywords
Presentation 2011-03-02 14:00
Exact, Fast and Flexible Two-level Cache Simulation for Embedded Systems
Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) VLD2010-118
Abstract (in Japanese) (See Japanese page) 
(in English) In hierarchical cache configurations, L1 cache uses LRU as cache
replacement policy but L2 and/or L3 caches use FIFO due to its low
hardware cost. This paper proposes a fast cache configuration simulation
method for hierarchical cache configurations composed of LRU-based
L1-cache and FIFO-based L2-cache. In our proposed method, we fix L1 data
cache and simulate several L1 instruction cache configurations and L2
unified cache configurations simultaneously with varying their cache
parameters. By using L1/L2 cache properties, we can skip to simulate
several cache configurations but can obtain exact cache hit/miss counts
for all the L1/L2 cache configurations. Experimental evaluations
demonstrate that our proposed method boosts up the simulation speed by
up to 1900 times.
Keyword (in Japanese) (See Japanese page) 
(in English) FIFO / cache simulation / cache memory / optimization of the cache structure / embedded systems / L2 cache / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 432, VLD2010-118, pp. 13-18, March 2011.
Paper # VLD2010-118 
Date of Issue 2011-02-23 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2010-118

Conference Information
Committee VLD  
Conference Date 2011-03-02 - 2011-03-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawaken-Danjo-Kyodo-Sankaku Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2011-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Exact, Fast and Flexible Two-level Cache Simulation for Embedded Systems 
Sub Title (in English)  
Keyword(1) FIFO  
Keyword(2) cache simulation  
Keyword(3) cache memory  
Keyword(4) optimization of the cache structure  
Keyword(5) embedded systems  
Keyword(6) L2 cache  
Keyword(7)  
Keyword(8)  
1st Author's Name Masashi Tawada  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Masao Yanagisawa  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Tatsuo Ohtsuki  
3rd Author's Affiliation Waseda University (Waseda Univ.)
4th Author's Name Nozomu Togawa  
4th Author's Affiliation Waseda University (Waseda Univ.)
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Speaker Author-1 
Date Time 2011-03-02 14:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2010-118 
Volume (vol) vol.110 
Number (no) no.432 
Page pp.13-18 
#Pages 6 
Date of Issue 2011-02-23 (VLD) 

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