Paper Abstract and Keywords |
Presentation |
2011-03-03 11:50
A scalable hardware architecture for real time image recognition Takashi Aoki, Eiichi Hosoya, Takuya Otsuka, Akira Onozawa (NTT) VLD2010-129 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A scalable hardware architecture is proposed for real time image recognition application.
The hardware creates feature values of the input images based on HOG algorithm, which are accepted by Real AdaBoost algorithm in the following recognition phase.
It achieves not only high throughput and low latency but can adjust itself flexibly to user requirements such as resolution of input images, recognition accuracy, and so on, by an efficient implementation of the weak classifiers.
We have implemented the hardware on FPGAs and verified its performance. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
real time image processing / image recognition / HOG / AdaBoost / FPGA / / / |
Reference Info. |
IEICE Tech. Rep., vol. 110, no. 432, VLD2010-129, pp. 75-80, March 2011. |
Paper # |
VLD2010-129 |
Date of Issue |
2011-02-23 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2010-129 |
Conference Information |
Committee |
VLD |
Conference Date |
2011-03-02 - 2011-03-04 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawaken-Danjo-Kyodo-Sankaku Center |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Technology for System-on-Silicon |
Paper Information |
Registration To |
VLD |
Conference Code |
2011-03-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A scalable hardware architecture for real time image recognition |
Sub Title (in English) |
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Keyword(1) |
real time image processing |
Keyword(2) |
image recognition |
Keyword(3) |
HOG |
Keyword(4) |
AdaBoost |
Keyword(5) |
FPGA |
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1st Author's Name |
Takashi Aoki |
1st Author's Affiliation |
NTT Microsystem Integration Laboratories (NTT) |
2nd Author's Name |
Eiichi Hosoya |
2nd Author's Affiliation |
NTT Microsystem Integration Laboratories (NTT) |
3rd Author's Name |
Takuya Otsuka |
3rd Author's Affiliation |
NTT Microsystem Integration Laboratories (NTT) |
4th Author's Name |
Akira Onozawa |
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NTT Microsystem Integration Laboratories (NTT) |
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Speaker |
Author-1 |
Date Time |
2011-03-03 11:50:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2010-129 |
Volume (vol) |
vol.110 |
Number (no) |
no.432 |
Page |
pp.75-80 |
#Pages |
6 |
Date of Issue |
2011-02-23 (VLD) |
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