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Paper Abstract and Keywords
Presentation 2011-03-03 10:20
Implementation and Security Evaluation of DPA-Resistant DES Circuit utilizing Domino-RSL technique
Katsuhiko Iwai, Kenji Kojima, Mitsuru Shiozaki, Syunsuke Asagawa, Takeshi Fujino (Ritsumeikan Univ.) VLD2010-126
Abstract (in Japanese) (See Japanese page) 
(in English) Some secure DPA-resistant techniques to protect from Side-Channel Attack such as Differential Power Analysis (DPA) have been proposed. However, these techniques can achieve DPA-resistance whereas special CADs are required to design cryptographic circuits. For example, the WDDL technique requires special CAD to balance wiring capacitance. And, the RSL technique requires special CAD to control the timing to activate the logics for enabling signals. We have proposed a DPA-resistant Domino-RSL technique, which can design and implement cryptographic circuits using the standard CAD tool easily. The DES circuit was designed and fabricated with 0.18μm CMOS technology. This paper presents the design flow and DPA-resistant evaluation results.
Keyword (in Japanese) (See Japanese page) 
(in English) Side-Channnel Attack / DPA / CPA / WDDL / RSL / Domino-RSL / Design Compiler / SIS  
Reference Info. IEICE Tech. Rep., vol. 110, no. 432, VLD2010-126, pp. 57-62, March 2011.
Paper # VLD2010-126 
Date of Issue 2011-02-23 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2010-126

Conference Information
Committee VLD  
Conference Date 2011-03-02 - 2011-03-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawaken-Danjo-Kyodo-Sankaku Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2011-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementation and Security Evaluation of DPA-Resistant DES Circuit utilizing Domino-RSL technique 
Sub Title (in English)  
Keyword(1) Side-Channnel Attack  
Keyword(2) DPA  
Keyword(3) CPA  
Keyword(4) WDDL  
Keyword(5) RSL  
Keyword(6) Domino-RSL  
Keyword(7) Design Compiler  
Keyword(8) SIS  
1st Author's Name Katsuhiko Iwai  
1st Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
2nd Author's Name Kenji Kojima  
2nd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
3rd Author's Name Mitsuru Shiozaki  
3rd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
4th Author's Name Syunsuke Asagawa  
4th Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
5th Author's Name Takeshi Fujino  
5th Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
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Speaker Author-1 
Date Time 2011-03-03 10:20:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2010-126 
Volume (vol) vol.110 
Number (no) no.432 
Page pp.57-62 
#Pages 6 
Date of Issue 2011-02-23 (VLD) 

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