Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2011-03-04 15:30
Performance Evaluation of Via Programmable ASIC Architecture VPEX3
Taisuke Ueoka, Tatsuya Kitamori, Ryohei Hori (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2010-146
Abstract (in Japanese) (See Japanese page) 
(in English) We have been studying via programmable ASIC architecture “VPEX” whose logic element (LE) consists of complex-gate type Exclusive-OR and NOT gates．In the conventional VPEX2, the 13 logic functions can be customized by via-1 layer, and the wiring between LEs are programmed by via-3 layer．In the new VPEX3 architecture proposed in the last year, the area of LE is decreased to 40%, and the number of configurable logic functions is increased to 22 kinds owing to applying via-2 as a programming layer. In this paper，we have developed the VPEX3 library used in Design Compiler, and evaluate the area and delay performance compared to conventional VPEX2 architecture and standard-cell based ASIC. As a result of evaluation，the area-delay product of VPEX3 is estimated as 35% of VPEX2, and twice of standard-cell based ASIC.
Keyword (in Japanese) (See Japanese page) 
(in English) Via Programmable / structured ASIC / Exclusive-OR / / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 432, VLD2010-146, pp. 177-182, March 2011.
Paper # VLD2010-146 
Date of Issue 2011-02-23 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2010-146

Conference Information
Committee VLD  
Conference Date 2011-03-02 - 2011-03-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawaken-Danjo-Kyodo-Sankaku Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2011-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Performance Evaluation of Via Programmable ASIC Architecture VPEX3 
Sub Title (in English)  
Keyword(1) Via Programmable  
Keyword(2) structured ASIC  
Keyword(3) Exclusive-OR  
Keyword(4)  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Taisuke Ueoka  
1st Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
2nd Author's Name Tatsuya Kitamori  
2nd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
3rd Author's Name Ryohei Hori  
3rd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
4th Author's Name Masaya Yoshikawa  
4th Author's Affiliation Meijo University (Meijo Univ.)
5th Author's Name Takeshi Fujino  
5th Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2011-03-04 15:30:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2010-146 
Volume (vol) vol.110 
Number (no) no.432 
Page pp.177-182 
#Pages 6 
Date of Issue 2011-02-23 (VLD) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan