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Paper Abstract and Keywords
Presentation 2011-03-18 10:55
Modeling of Timing Faults and Test Generation for Single Flux Quantum Logic Circuits
Nobutaka Kito (Kyoto Univ.), Kazuyoshi Takagi (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) CPSY2010-74 DC2010-73
Abstract (in Japanese) (See Japanese page) 
(in English) Single Flux Quqntum(SFQ) logic circuits are expected to achieve
ultra-high-performance computers with low power.
For realizing SFQ high-performance computers,
fundamental technologies of SFQ super computers have been studied intensively.
This report discusses fault modeling and test generation for SFQ logic circuits.
SFQ circuits are very fast and use special logic system (pulse logic).
Therefore,
SFQ specific faults different from faults of CMOS logic circuits exists
such as misalignment of data arrival clock cycle at gate inputs.
In this report, a fault model for SFQ circuits and a test generation method with respect to the fault model are shown.
In test generation, SFQ circuits are classified according to circuit structure of reconvergence.
Two types of SFQ circuits are shown.
For each type, test generation method is proposed.
Keyword (in Japanese) (See Japanese page) 
(in English) Single flux quantum circuit / SFQ circuit / testing / timing fault / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 474, DC2010-73, pp. 51-56, March 2011.
Paper # DC2010-73 
Date of Issue 2011-03-11 (CPSY, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2010-74 DC2010-73

Conference Information
Committee CPSY DC IPSJ-SLDM IPSJ-EMB  
Conference Date 2011-03-18 - 2011-03-19 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2011-03-CPSY-DC-SLDM-EMB 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Modeling of Timing Faults and Test Generation for Single Flux Quantum Logic Circuits 
Sub Title (in English)  
Keyword(1) Single flux quantum circuit  
Keyword(2) SFQ circuit  
Keyword(3) testing  
Keyword(4) timing fault  
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Keyword(6)  
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1st Author's Name Nobutaka Kito  
1st Author's Affiliation Kyoto University (Kyoto Univ.)
2nd Author's Name Kazuyoshi Takagi  
2nd Author's Affiliation Nagoya University (Nagoya Univ.)
3rd Author's Name Naofumi Takagi  
3rd Author's Affiliation Kyoto University (Kyoto Univ.)
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Speaker Author-1 
Date Time 2011-03-18 10:55:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # CPSY2010-74, DC2010-73 
Volume (vol) vol.110 
Number (no) no.473(CPSY), no.474(DC) 
Page pp.51-56 
#Pages 6 
Date of Issue 2011-03-11 (CPSY, DC) 

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