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Paper Abstract and Keywords
Presentation 2011-04-19 11:45
Suppress of Half Select Disturb in 8T-SRAM by Local Injected Electron Asymmetric Pass Gate Transistor
Kousuke Miyaji, Kentaro Honda, Shuhei Tanakamaru (Univ. of Tokyo), Shinji Miyano (STARC), Ken Takeuchi (Univ. of Tokyo) ICD2011-13
Abstract (in Japanese) (See Japanese page) 
(in English) 8T-SRAM cell with asymmetric pass gate transistor by local electron injection is proposed to solve half select disturb. Two types of electron injection scheme: both side injection scheme and self-repair one side injection scheme are analyzed comprehensively for 65nm technology node 8T-SRAM cell and also for 6T-SRAM cell. This paper shows that in the 6T-SRAM with the local injected electrons [1] the read speed degrades by as much as 6.3 times. In contrast, the proposed 8T-SRAM cell with the self-repair one side injection scheme is most suitable to solve the conflict of the half select disturb, write disturb and read speed. In the proposed 8T-SRAM, the disturb margin increases by 141% without write margin or read speed degradation. The proposed scheme has no process or area penalty compared with the standard CMOS-process 8T-SRAM.
Keyword (in Japanese) (See Japanese page) 
(in English) SRAM / 8T-SRAM / Local electron injection / Half select disturb / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 6, ICD2011-13, pp. 71-76, April 2011.
Paper # ICD2011-13 
Date of Issue 2011-04-11 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ICD  
Conference Date 2011-04-18 - 2011-04-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Kobe University Takigawa Memorial Hall 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Memory Device Technologies 
Paper Information
Registration To ICD 
Conference Code 2011-04-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Suppress of Half Select Disturb in 8T-SRAM by Local Injected Electron Asymmetric Pass Gate Transistor 
Sub Title (in English)  
Keyword(1) SRAM  
Keyword(2) 8T-SRAM  
Keyword(3) Local electron injection  
Keyword(4) Half select disturb  
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1st Author's Name Kousuke Miyaji  
1st Author's Affiliation University of Tokyo (Univ. of Tokyo)
2nd Author's Name Kentaro Honda  
2nd Author's Affiliation University of Tokyo (Univ. of Tokyo)
3rd Author's Name Shuhei Tanakamaru  
3rd Author's Affiliation University of Tokyo (Univ. of Tokyo)
4th Author's Name Shinji Miyano  
4th Author's Affiliation Semiconductor Technology Academic Research Center (STARC)
5th Author's Name Ken Takeuchi  
5th Author's Affiliation University of Tokyo (Univ. of Tokyo)
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Speaker Author-1 
Date Time 2011-04-19 11:45:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2011-13 
Volume (vol) vol.111 
Number (no) no.6 
Page pp.71-76 
#Pages
Date of Issue 2011-04-11 (ICD) 


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