IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2011-06-24 13:00
An Approach and Evaluation of Fault Tolerant Sequential Circuits for Simultaneous Occurrence of Multiple Transient Faults
Satoshi Fukumoto, Masayuki Arai, Shinya Hara, Kazuhiko Iwasaki (TMU) DC2011-8
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we analyze the distribution of fault coverage in random-pattern testing. We introduce a stochastic variable that maps the events of detection and non-detection of each fault in a random-pattern testing into the integers 1 and 0 respectively. Based on this variable, we establish a stochastic evaluation model and numerically show that mean and variance of fault coverage distribution can be estimated precisely from the anaytical results.
Keyword (in Japanese) (See Japanese page) 
(in English) fault coverage / ramdom-pattern testing / stochastic model / / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 100, DC2011-8, pp. 1-4, June 2011.
Paper # DC2011-8 
Date of Issue 2011-06-17 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Notes on Review This article is a technical report without peer review, and its polished version will be published elsewhere.
Download PDF DC2011-8

Conference Information
Committee DC  
Conference Date 2011-06-24 - 2011-06-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design, Test, Verification 
Paper Information
Registration To DC 
Conference Code 2011-06-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Approach and Evaluation of Fault Tolerant Sequential Circuits for Simultaneous Occurrence of Multiple Transient Faults 
Sub Title (in English)  
Keyword(1) fault coverage  
Keyword(2) ramdom-pattern testing  
Keyword(3) stochastic model  
Keyword(4)  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Satoshi Fukumoto  
1st Author's Affiliation Tokyo Metropolitan University (TMU)
2nd Author's Name Masayuki Arai  
2nd Author's Affiliation Tokyo Metropolitan University (TMU)
3rd Author's Name Shinya Hara  
3rd Author's Affiliation Graduate School of System Design, Tokyo Metropolitan University (TMU)
4th Author's Name Kazuhiko Iwasaki  
4th Author's Affiliation Tokyo Metropolitan University (TMU)
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-2 
Date Time 2011-06-24 13:00:00 
Presentation Time 30 minutes 
Registration for DC 
Paper # DC2011-8 
Volume (vol) vol.111 
Number (no) no.100 
Page pp.1-4 
#Pages
Date of Issue 2011-06-17 (DC) 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan