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| Presentation | 2011-07-21 09:30 A Level Shifter with Logic Error Correction Circuit for Low-Voltage Digital LSIs Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.)  ICD2011-21 Link to ES Tech. Rep. Archives: ICD2011-21 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A level shifter circuit capable of extremely low-voltage inputs is presented in this paper. The circuit consists of a level conversion circuit and a logic error correction circuit. The level conversion circuit generates output voltage signal according to the voltage difference between complementary input signals. The logic error correction circuit has a distinctive feature in current generation scheme by detecting input and output logic levels. The proposed circuit can convert low-voltage input digital signals into high-voltage output digital signals. The circuit achieves low-power operation because it dissipates operating current only when the input signals change. Measurement results demonstrated that the circuit can convert low-voltage input signals of 0.4 V into 3 V output signals. The power dissipation was 58 nW at 0.4-V and 10-kHz input pulse. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Level shifter / Low voltage operation / Low power dissipation / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 111, no. 151, ICD2011-21, pp. 1-6, July 2011. | |
| Paper # | ICD2011-21 | |
| Date of Issue | 2011-07-14 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ICD2011-21 Link to ES Tech. Rep. Archives: ICD2011-21 |
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| Conference Information | |
| Committee | ICD ITE-IST |
| Conference Date | 2011-07-21 - 2011-07-22 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hiroshima Institute of Technology |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Analog, Mixed analog and digital, RF, and sensor interface circuitry |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2011-07-ICD-IST |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Level Shifter with Logic Error Correction Circuit for Low-Voltage Digital LSIs |
| Sub Title (in English) | |
| Keyword(1) | Level shifter |
| Keyword(2) | Low voltage operation |
| Keyword(3) | Low power dissipation |
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| 1st Author's Name | Yuji Osaki |
| 1st Author's Affiliation | Kobe University (Kobe Univ.) |
| 2nd Author's Name | Tetsuya Hirose |
| 2nd Author's Affiliation | Kobe University (Kobe Univ.) |
| 3rd Author's Name | Nobutaka Kuroki |
| 3rd Author's Affiliation | Kobe University (Kobe Univ.) |
| 4th Author's Name | Masahiro Numa |
| 4th Author's Affiliation | Kobe University (Kobe Univ.) |
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| Speaker | Author-1 |
| Date Time | 2011-07-21 09:30:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | ICD2011-21 |
| Volume (vol) | vol.111 |
| Number (no) | no.151 |
| Page | pp.1-6 |
| #Pages | 6 |
| Date of Issue | 2011-07-14 (ICD) |
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