講演抄録/キーワード |
講演名 |
2011-09-26 15:30
Preemptive Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs - Hardware and Reconfiguration Layers ○Krzysztof Jozwik・Shinya Honda(Nagoya Univ.)・Hiroyuki Tomiyama(Ritsumeikan Univ.)・Hiroaki Takada(Nagoya Univ.) RECONF2011-29 |
抄録 |
(和) |
Preemption techniques for HW (hardware) tasks
have been studied in order to improve their responsiveness
and to allow implementation of a blocking call within a task.
In order to support preemption of HW tasks at a level of
a conventional software multitasking OS, context saving and
restoring mechanisms must be implemented in hardware and
appropriate software programming interface, abstracting their
implementation details, provided. This paper presents a solution
for efficient preemptive hardware multitasking on Xilinx Virtex
FPGAs. It comprises an embedded system framework and design
flow back-end tools which automate generation of preemptable
HW tasks and configuration files used by the framework. The
framework features in a high-speed reconfiguration/readback
controller and a low-footprint configuration layer. The layer
provides an easy-to-use API (Application Programming Interface)
facilitating management of the preemption process, which
could be used as a base of a fully fledged preemptive SW/HW
multitasking OS. The framework has been implemented on top
of the Virtex-4 FPGAs and showed promising results. |
(英) |
Preemption techniques for HW (hardware) tasks
have been studied in order to improve their responsiveness
and to allow implementation of a blocking call within a task.
In order to support preemption of HW tasks at a level of
a conventional software multitasking OS, context saving and
restoring mechanisms must be implemented in hardware and
appropriate software programming interface, abstracting their
implementation details, provided. This paper presents a solution
for efficient preemptive hardware multitasking on Xilinx Virtex
FPGAs. It comprises an embedded system framework and design
flow back-end tools which automate generation of preemptable
HW tasks and configuration files used by the framework. The
framework features in a high-speed reconfiguration/readback
controller and a low-footprint configuration layer. The layer
provides an easy-to-use API (Application Programming Interface)
facilitating management of the preemption process, which
could be used as a base of a fully fledged preemptive SW/HW
multitasking OS. The framework has been implemented on top
of the Virtex-4 FPGAs and showed promising results. |
キーワード |
(和) |
run-time reconfiguration / dynamic reconfiguration / FPGA / / / / / |
(英) |
run-time reconfiguration / dynamic reconfiguration / FPGA / / / / / |
文献情報 |
信学技報, vol. 111, no. 218, RECONF2011-29, pp. 43-48, 2011年9月. |
資料番号 |
RECONF2011-29 |
発行日 |
2011-09-19 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
PDFダウンロード |
RECONF2011-29 |