Paper Abstract and Keywords |
Presentation |
2011-09-26 15:30
Preemptive Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs - Hardware and Reconfiguration Layers Krzysztof Jozwik, Shinya Honda (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) RECONF2011-29 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Preemption techniques for HW (hardware) tasks
have been studied in order to improve their responsiveness
and to allow implementation of a blocking call within a task.
In order to support preemption of HW tasks at a level of
a conventional software multitasking OS, context saving and
restoring mechanisms must be implemented in hardware and
appropriate software programming interface, abstracting their
implementation details, provided. This paper presents a solution
for efficient preemptive hardware multitasking on Xilinx Virtex
FPGAs. It comprises an embedded system framework and design
flow back-end tools which automate generation of preemptable
HW tasks and configuration files used by the framework. The
framework features in a high-speed reconfiguration/readback
controller and a low-footprint configuration layer. The layer
provides an easy-to-use API (Application Programming Interface)
facilitating management of the preemption process, which
could be used as a base of a fully fledged preemptive SW/HW
multitasking OS. The framework has been implemented on top
of the Virtex-4 FPGAs and showed promising results. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
run-time reconfiguration / dynamic reconfiguration / FPGA / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 218, RECONF2011-29, pp. 43-48, Sept. 2011. |
Paper # |
RECONF2011-29 |
Date of Issue |
2011-09-19 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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RECONF2011-29 |
Conference Information |
Committee |
RECONF |
Conference Date |
2011-09-26 - 2011-09-27 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Nagoya Univ. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Reconfigurable Systems, etc. |
Paper Information |
Registration To |
RECONF |
Conference Code |
2011-09-RECONF |
Language |
English |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Preemptive Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs - Hardware and Reconfiguration Layers |
Sub Title (in English) |
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Keyword(1) |
run-time reconfiguration |
Keyword(2) |
dynamic reconfiguration |
Keyword(3) |
FPGA |
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1st Author's Name |
Krzysztof Jozwik |
1st Author's Affiliation |
Nagoya University (Nagoya Univ.) |
2nd Author's Name |
Shinya Honda |
2nd Author's Affiliation |
Nagoya University (Nagoya Univ.) |
3rd Author's Name |
Hiroyuki Tomiyama |
3rd Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
4th Author's Name |
Hiroaki Takada |
4th Author's Affiliation |
Nagoya University (Nagoya Univ.) |
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Speaker |
Author-1 |
Date Time |
2011-09-26 15:30:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
RECONF2011-29 |
Volume (vol) |
vol.111 |
Number (no) |
no.218 |
Page |
pp.43-48 |
#Pages |
6 |
Date of Issue |
2011-09-19 (RECONF) |
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