Paper Abstract and Keywords |
Presentation |
2011-09-27 13:45
Performance Comparison of the Pattern-Recognition Hardware Using Data-Direct-Implementation Approach Yusuke Sato, Moritoshi Yasunaga, Noriyuki Aibe (Univ. of Tsukuba) RECONF2011-39 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We have proposed a novel architecture called “Direct Data Implementation (DDI)” aiming for a super high-speed recognition system. DDI is composed of dedicated circuits that have the same parallelism as the number of sample patterns by embedding known patterns directly to logic circuits. In this paper, we evaluated the power consumption, processing speed and circuit size of DDI implemented in the FPGAs on the prototype board made in the latest report. As a result, we have measured that DDI requires about 1/74 times less energy ,120 times higher processing speed and about 1.4 times larger circuit size than the traditional parallel pattern recognition circuits. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA / Pattern Recognition / Parallel Processing / Power Consumption / Circuit Size / Processing Speed / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 218, RECONF2011-39, pp. 99-104, Sept. 2011. |
Paper # |
RECONF2011-39 |
Date of Issue |
2011-09-19 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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RECONF2011-39 |
Conference Information |
Committee |
RECONF |
Conference Date |
2011-09-26 - 2011-09-27 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Nagoya Univ. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Reconfigurable Systems, etc. |
Paper Information |
Registration To |
RECONF |
Conference Code |
2011-09-RECONF |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Performance Comparison of the Pattern-Recognition Hardware Using Data-Direct-Implementation Approach |
Sub Title (in English) |
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Keyword(1) |
FPGA |
Keyword(2) |
Pattern Recognition |
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Parallel Processing |
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Power Consumption |
Keyword(5) |
Circuit Size |
Keyword(6) |
Processing Speed |
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1st Author's Name |
Yusuke Sato |
1st Author's Affiliation |
University of Tsukuba (Univ. of Tsukuba) |
2nd Author's Name |
Moritoshi Yasunaga |
2nd Author's Affiliation |
University of Tsukuba (Univ. of Tsukuba) |
3rd Author's Name |
Noriyuki Aibe |
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University of Tsukuba (Univ. of Tsukuba) |
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Speaker |
Author-1 |
Date Time |
2011-09-27 13:45:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
RECONF2011-39 |
Volume (vol) |
vol.111 |
Number (no) |
no.218 |
Page |
pp.99-104 |
#Pages |
6 |
Date of Issue |
2011-09-19 (RECONF) |
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