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| Presentation | 2011-10-20 14:20 Fast Simulation of Multiconductor System with Nonlinear Devices by Using Block-Latency Insertion Method and Reduced Order Model Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.)  CAS2011-41 NLP2011-68 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper describes a fast circuit simulation technique based on the block-latency insertion method (block-LIM) and a model order reduction (MOR) technique. The block-LIM is one of the efficient transient analysis methods adopting an explicit leapfrog finite difference method. In the block-LIM, due to duality of voltage and current variables, they are successfully separated from each other by using a staggered time step placement. Thus, each of them can be updated individually within a local block through a time stepping procedure. In this work, we build a reduced order model of the partitioned local block to improve the efficiency of the block-LIM. Compared to other circuit partitioning techniques coupled with the MOR, the order-reduced block-LIM can easily decrease whole computational costs of the transient simulation. Numerical results show that our approach is adequate for the fast simulation of tightly coupled multiconductor transmission lines with CMOS inverters. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | block latency insertion method / CMOS inverter / fast circuit simulation / model order reduction / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 111, no. 242, CAS2011-41, pp. 49-54, Oct. 2011. | |
| Paper # | CAS2011-41 | |
| Date of Issue | 2011-10-13 (CAS, NLP) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CAS2011-41 NLP2011-68 |
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| Conference Information | |
| Committee | CAS NLP |
| Conference Date | 2011-10-20 - 2011-10-21 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Shizuoka Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Circuit and System, etc. |
| Paper Information | |
| Registration To | CAS |
| Conference Code | 2011-10-CAS-NLP |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Fast Simulation of Multiconductor System with Nonlinear Devices by Using Block-Latency Insertion Method and Reduced Order Model |
| Sub Title (in English) | |
| Keyword(1) | block latency insertion method |
| Keyword(2) | CMOS inverter |
| Keyword(3) | fast circuit simulation |
| Keyword(4) | model order reduction |
| Keyword(5) | |
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| 1st Author's Name | Tadatoshi Sekine |
| 1st Author's Affiliation | Shizuoka University (Shizuoka Univ.) |
| 2nd Author's Name | Hideki Asai |
| 2nd Author's Affiliation | Shizuoka University (Shizuoka Univ.) |
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| Speaker | Author-1 |
| Date Time | 2011-10-20 14:20:00 |
| Presentation Time | 25 minutes |
| Registration for | CAS |
| Paper # | CAS2011-41, NLP2011-68 |
| Volume (vol) | vol.111 |
| Number (no) | no.242(CAS), no.243(NLP) |
| Page | pp.49-54 |
| #Pages | 6 |
| Date of Issue | 2011-10-13 (CAS, NLP) |
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