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Paper Abstract and Keywords
Presentation 2011-10-24 14:45
Architecture of a Dynamically Reconfigurable VLSI Processor Based on Register-Transfer-Level Packet Transfer
Yoshichika Fujioka (Hachinohe Inst. of Tech.), Sho Takizawa, Michitaka Kameyama (Tohoku Univ.) SIP2011-64 ICD2011-67 IE2011-63
Abstract (in Japanese) (See Japanese page) 
(in English) Register-transfer-level packet routing scheme is proposed for intra-chip data transfer to make the size of configuration memory for dynamically reconfigurable VLSI processors greatly reduced. Configuration memory reduction in the conventional dynamically reconfigurable parallel VLSI processor can be achieved based on semi-autonomous packet routing, where both autonomous packet data transfer and offline scheduling/allocation are effectively utilized. Dynamic reconfiguration of local memories is also introduced to utilize the control memory resources. According to requirement of the local memory capacity for each PE, partial crossbar switches are controlled by the packet destination address information. It is demonstrated that the packet-routing control storage capacity can be reduced to about 1/10 in some parallel processing example compared to the conventional dynamically reconfigurable VLSI.
Keyword (in Japanese) (See Japanese page) 
(in English) coarse-grain reconfigurable VLSI processor / semi-autonomous packet routing / dynamic reconfiguration of local memories / configuration memory / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 258, ICD2011-67, pp. 13-18, Oct. 2011.
Paper # ICD2011-67 
Date of Issue 2011-10-17 (SIP, ICD, IE) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SIP2011-64 ICD2011-67 IE2011-63

Conference Information
Committee ICD IE SIP IPSJ-SLDM  
Conference Date 2011-10-24 - 2011-10-25 
Place (in Japanese) (See Japanese page) 
Place (in English) Ｉｃｈｉｎｏｂｏ(Sendai) 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2011-10-ICD-IE-SIP-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Architecture of a Dynamically Reconfigurable VLSI Processor Based on Register-Transfer-Level Packet Transfer 
Sub Title (in English)  
Keyword(1) coarse-grain reconfigurable VLSI processor  
Keyword(2) semi-autonomous packet routing  
Keyword(3) dynamic reconfiguration of local memories  
Keyword(4) configuration memory  
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1st Author's Name Yoshichika Fujioka  
1st Author's Affiliation Hachinohe Institute of Technology (Hachinohe Inst. of Tech.)
2nd Author's Name Sho Takizawa  
2nd Author's Affiliation Tohoku University (Tohoku Univ.)
3rd Author's Name Michitaka Kameyama  
3rd Author's Affiliation Tohoku University (Tohoku Univ.)
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Speaker Author-1 
Date Time 2011-10-24 14:45:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # SIP2011-64, ICD2011-67, IE2011-63 
Volume (vol) vol.111 
Number (no) no.257(SIP), no.258(ICD), no.259(IE) 
Page pp.13-18 
#Pages 6 
Date of Issue 2011-10-17 (SIP, ICD, IE) 

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