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Paper Abstract and Keywords
Presentation 2011-11-28 13:50
A Dynamically Configurable NoC Test Access Mechanism
Takieddine Sbiai, Kazuteru Namba, Hideo Ito (Chiba Univ.) VLD2011-60 DC2011-36
Abstract (in Japanese) (See Japanese page) 
(in English) When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses form cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focuses on reusing the NoC as TAM, in which, communication infrastructure (routers, interconnection links, protocols…) is reused as TAM. While NoC reuse as TAM can achieve a low area overhead, test scheduling is a difficult issue, due to the fact that test data is exchanged in packets. Based on this drawback, this paper presents a new dynamically configurable NoC TAM. On the one hand it could be considered as a NoC reuse as TAM because of using the already existing communication infrastructure. On the other hand, it can be configured as traditional TAM architecture, in which CUTs are directly connected to the automated test equipment (ATE) just like in traditional SoC testing. This configurability allows us to have the granularity of the traditional TAM which facilitate test scheduling, and the advantages of the NoC communication infrastructure, which gives us the possibility of parallel testing, low area overhead and usage of the functional NoC frequencies. The proposed TAM is then compared to a conventional NoC reuse as TAM methods and a TAM architecture named T2-TAM using two ITC’02 benchmark circuits. The presented results show a test time reduction between 17% and 55% while imposing a 9.6% area overhead.
Keyword (in Japanese) (See Japanese page) 
(in English) NoC / Test Access Mechanism / NoC reuse as TAM / Dynamically configured TAM / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 325, DC2011-36, pp. 49-54, Nov. 2011.
Paper # DC2011-36 
Date of Issue 2011-11-21 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2011-60 DC2011-36

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2011-11-28 - 2011-11-30 
Place (in Japanese) (See Japanese page) 
Place (in English) NewWelCity Miyazaki 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2010 -New Field of VLSI Design- 
Paper Information
Registration To DC 
Conference Code 2011-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Dynamically Configurable NoC Test Access Mechanism 
Sub Title (in English)  
Keyword(1) NoC  
Keyword(2) Test Access Mechanism  
Keyword(3) NoC reuse as TAM  
Keyword(4) Dynamically configured TAM  
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1st Author's Name Takieddine Sbiai  
1st Author's Affiliation Chiba University (Chiba Univ.)
2nd Author's Name Kazuteru Namba  
2nd Author's Affiliation Chiba University (Chiba Univ.)
3rd Author's Name Hideo Ito  
3rd Author's Affiliation Chiba University (Chiba Univ.)
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Speaker Author-1 
Date Time 2011-11-28 13:50:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # VLD2011-60, DC2011-36 
Volume (vol) vol.111 
Number (no) no.324(VLD), no.325(DC) 
Page pp.49-54 
#Pages 6 
Date of Issue 2011-11-21 (VLD, DC) 

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