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| Presentation | 2011-11-30 09:00 A Circuit Partitioning Strategy for 3-D Integrated Floating-point Multipliers Kazushige Kawai, Jubee Tada (Yamagata Univ.), Ryusuke Egawa, Hiroaki Kobayashi (Tohoku Univ.), Gensuke Goto (Yamagata Univ.)  CPM2011-162 ICD2011-94 Link to ES Tech. Rep. Archives: CPM2011-162 ICD2011-94 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Three-dimensional (3-D) integration technologies are attractive for enhancing the speed of the arithmetic circuits. To implement 3-D stacked arithmetic units, effective circuit–partitioning strategies should be applied to exploit the potential of 3-D integration technologies. In this paper, we target a single-precision and a double-precision floating-point multipliers for speed-up the circuit2 by using 3-D integration. Our partitioning strategy is that the parts of the critical-path circuits for multiplication, normalizer and rounder are implemented on the same layer, avoiding to use TSV. The simulation analysis shows that the delay time reduces to 92% for a single-precision and 83% for a double-precision multipliers, as compared with those of the conventional 2-D floating-point multipliers | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | 3-D integration / floating-point multiplier / / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 111, no. 327, ICD2011-94, pp. 67-72, Nov. 2011. | |
| Paper # | ICD2011-94 | |
| Date of Issue | 2011-11-21 (CPM, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPM2011-162 ICD2011-94 Link to ES Tech. Rep. Archives: CPM2011-162 ICD2011-94 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2011-11-28 - 2011-11-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | NewWelCity Miyazaki |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2010 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2011-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Circuit Partitioning Strategy for 3-D Integrated Floating-point Multipliers |
| Sub Title (in English) | |
| Keyword(1) | 3-D integration |
| Keyword(2) | floating-point multiplier |
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| 1st Author's Name | Kazushige Kawai |
| 1st Author's Affiliation | Yamagata University (Yamagata Univ.) |
| 2nd Author's Name | Jubee Tada |
| 2nd Author's Affiliation | Yamagata University (Yamagata Univ.) |
| 3rd Author's Name | Ryusuke Egawa |
| 3rd Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 4th Author's Name | Hiroaki Kobayashi |
| 4th Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 5th Author's Name | Gensuke Goto |
| 5th Author's Affiliation | Yamagata University (Yamagata Univ.) |
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| Speaker | Author-1 |
| Date Time | 2011-11-30 09:00:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | CPM2011-162, ICD2011-94 |
| Volume (vol) | vol.111 |
| Number (no) | no.326(CPM), no.327(ICD) |
| Page | pp.67-72 |
| #Pages | 6 |
| Date of Issue | 2011-11-21 (CPM, ICD) |
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