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Paper Abstract and Keywords
Presentation 2011-12-15 16:10
[Poster Presentation] A Implementation Technique of a Multibit Successive Approximation Register AD Converter
Naoya Kunikata, Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.) ICD2011-107
Abstract (in Japanese) (See Japanese page) 
(in English) A multibit SAR(Successive Approximation Register)-ADC is presented.Recent growth of the portable device market requires a low power and a high speed ADC.A SAR-ADC is suitable for low power applications, however the conversion speed is very slow.Multibit operation of SAR-ADC improves operation speed. The problem of multibit SAR-ADC is how to provide multiple reference voltages.In this study, an implementation technique of multibit SAR-ADC using capacitor efficient sub-DAC to provide multiple reference voltages is proposed.
Keyword (in Japanese) (See Japanese page) 
(in English) SAR-ADC / 4input comparator / multibit / ADC / high speed / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 352, ICD2011-107, pp. 41-45, Dec. 2011.
Paper # ICD2011-107 
Date of Issue 2011-12-08 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2011-107

Conference Information
Committee ICD  
Conference Date 2011-12-15 - 2011-12-16 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2011-12-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Implementation Technique of a Multibit Successive Approximation Register AD Converter 
Sub Title (in English)  
Keyword(1) SAR-ADC  
Keyword(2) 4input comparator  
Keyword(3) multibit  
Keyword(4) ADC  
Keyword(5) high speed  
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Keyword(8)  
1st Author's Name Naoya Kunikata  
1st Author's Affiliation Osaka University (Osaka Univ.)
2nd Author's Name Toshimasa Matsuoka  
2nd Author's Affiliation Osaka University (Osaka Univ.)
3rd Author's Name Kenji Taniguchi  
3rd Author's Affiliation Osaka University (Osaka Univ.)
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Speaker Author-1 
Date Time 2011-12-15 16:10:00 
Presentation Time 110 minutes 
Registration for ICD 
Paper # ICD2011-107 
Volume (vol) vol.111 
Number (no) no.352 
Page pp.41-45 
#Pages 5 
Date of Issue 2011-12-08 (ICD) 

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