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Paper Abstract and Keywords
Presentation 2012-01-25 10:00
Hardware TCP/IP Stack FPGA IP Core for Accelerating WEB Applications
Kotoko Fujita, Nadav Bergstein, Hakaru Tamukoh, Masatoshi Sekine (TUAT) VLD2011-91 CPSY2011-54 RECONF2011-50
Abstract (in Japanese) (See Japanese page) 
(in English) The implementation of TCP/IP is required for various embedded applications to connect into the Internet. However, software implementation with embedded CPU lacks the performance of processing speed and ASIC
implementation is less in exibility. In this paper, we propose an FPGA TCP/IP Stack. The hardware implementation of TCP/IP is directly connected to WEB application. In addition to previous works, we implement ICMP and TCP option including MSS, Window Scale and TimeStamp. Experimental results show that the proposed FPGA TCP/IP Stack achieves 95 Mbps actual performance, while the theoretical performance is 100 Mbps. Moreover, a WEB streaming demonstration system, which is constructed with the FPGA TCP/IP Stack and a circuit of video compression and extension, proceses the image (VGA Full color) about 20fps and achieves 30 times improvement in calculation speed over the existing similar software implementation.
Keyword (in Japanese) (See Japanese page) 
(in English) TCP/IP / TOE / hw/sw complex system / FPGA / WEB application / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 397, VLD2011-91, pp. 1-6, Jan. 2012.
Paper # VLD2011-91 
Date of Issue 2012-01-18 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2011-91 CPSY2011-54 RECONF2011-50

Conference Information
Committee VLD CPSY RECONF IPSJ-SLDM  
Conference Date 2012-01-25 - 2012-01-26 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To VLD 
Conference Code 2012-01-VLD-CPSY-RECONF-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Hardware TCP/IP Stack FPGA IP Core for Accelerating WEB Applications 
Sub Title (in English)  
Keyword(1) TCP/IP  
Keyword(2) TOE  
Keyword(3) hw/sw complex system  
Keyword(4) FPGA  
Keyword(5) WEB application  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Kotoko Fujita  
1st Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
2nd Author's Name Nadav Bergstein  
2nd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
3rd Author's Name Hakaru Tamukoh  
3rd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
4th Author's Name Masatoshi Sekine  
4th Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
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Speaker Author-1 
Date Time 2012-01-25 10:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2011-91, CPSY2011-54, RECONF2011-50 
Volume (vol) vol.111 
Number (no) no.397(VLD), no.398(CPSY), no.399(RECONF) 
Page pp.1-6 
#Pages
Date of Issue 2012-01-18 (VLD, CPSY, RECONF) 


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