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Paper Abstract and Keywords
Presentation 2012-01-26 14:20
Implementation of Numerical Circuit on 3D FPGA-Array
Kenichi Takahashi, Jiang Li, Yusuke Atsumari, Shunsuke Shimazaki, Hakaru Tamukoh, Masatoshi Sekine (TUAT) VLD2011-115 CPSY2011-78 RECONF2011-74
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, High Performance Computing (HPC) is increasingly used in various fields. HPC systems require both the flexibility and the low power consumption. In order to realize these requests, we have proposed a HPC system using a three-dimensional FPGA-Array. The 3D FPGA-Array is constructed by connecting small FPGA cards equip with three-dimensional I/O directions. It is possible to change its scale (i.e. number of FPGA cards) depending on the amount of calculation. In this paper, we implement a numerical circuit of Poisson's equation and Advection equation into the system, and discuss the performance.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA-Array / Reconfigurable HPC / Numerical Circuit / / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 397, VLD2011-115, pp. 141-146, Jan. 2012.
Paper # VLD2011-115 
Date of Issue 2012-01-18 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2011-115 CPSY2011-78 RECONF2011-74

Conference Information
Committee VLD CPSY RECONF IPSJ-SLDM  
Conference Date 2012-01-25 - 2012-01-26 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To VLD 
Conference Code 2012-01-VLD-CPSY-RECONF-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementation of Numerical Circuit on 3D FPGA-Array 
Sub Title (in English)  
Keyword(1) FPGA-Array  
Keyword(2) Reconfigurable HPC  
Keyword(3) Numerical Circuit  
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1st Author's Name Kenichi Takahashi  
1st Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
2nd Author's Name Jiang Li  
2nd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
3rd Author's Name Yusuke Atsumari  
3rd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
4th Author's Name Shunsuke Shimazaki  
4th Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
5th Author's Name Hakaru Tamukoh  
5th Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
6th Author's Name Masatoshi Sekine  
6th Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
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Speaker Author-1 
Date Time 2012-01-26 14:20:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2011-115, CPSY2011-78, RECONF2011-74 
Volume (vol) vol.111 
Number (no) no.397(VLD), no.398(CPSY), no.399(RECONF) 
Page pp.141-146 
#Pages 6 
Date of Issue 2012-01-18 (VLD, CPSY, RECONF) 

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