Paper Abstract and Keywords |
Presentation |
2012-01-26 11:15
Error Checker using Binary tree structure of Residue Signed-Digit Additions Qian Liu, Kazuhiro Motegi, Shugang Wei (Gunma Univ.) VLD2011-111 CPSY2011-74 RECONF2011-70 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this paper, a fast residue checker for error detection of arithmetic circuits is presented. The residue checker consists of SD residue adders, SD residue multipliers and binary-to-residue converters. New addition rules are used for generating the intermediate sum and carry with a binary number representation, and the error checker has a binary
tree structure of radix-two signed-digit number modulo $m (m=2^{p}+1)$ adders. We also try to find the optimum relationship between an n-bit binary number and a p-digit SD residue number. By using the presented residue arithmetic circuits, the error detection can be performed in real-time for a large product-sum circuit. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Error detection / SD(Signed-Digit) number representation / residue arithmetic / binary tree / residue checker / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 397, VLD2011-111, pp. 117-121, Jan. 2012. |
Paper # |
VLD2011-111 |
Date of Issue |
2012-01-18 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2011-111 CPSY2011-74 RECONF2011-70 |
Conference Information |
Committee |
VLD CPSY RECONF IPSJ-SLDM |
Conference Date |
2012-01-25 - 2012-01-26 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hiyoshi Campus, Keio University |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
FPGA Applications, etc |
Paper Information |
Registration To |
VLD |
Conference Code |
2012-01-VLD-CPSY-RECONF-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Error Checker using Binary tree structure of Residue Signed-Digit Additions |
Sub Title (in English) |
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Keyword(1) |
Error detection |
Keyword(2) |
SD(Signed-Digit) number representation |
Keyword(3) |
residue arithmetic |
Keyword(4) |
binary tree |
Keyword(5) |
residue checker |
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1st Author's Name |
Qian Liu |
1st Author's Affiliation |
Gunma University (Gunma Univ.) |
2nd Author's Name |
Kazuhiro Motegi |
2nd Author's Affiliation |
Gunma University (Gunma Univ.) |
3rd Author's Name |
Shugang Wei |
3rd Author's Affiliation |
Gunma University (Gunma Univ.) |
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Speaker |
Author-1 |
Date Time |
2012-01-26 11:15:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2011-111, CPSY2011-74, RECONF2011-70 |
Volume (vol) |
vol.111 |
Number (no) |
no.397(VLD), no.398(CPSY), no.399(RECONF) |
Page |
pp.117-121 |
#Pages |
5 |
Date of Issue |
2012-01-18 (VLD, CPSY, RECONF) |
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