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| Presentation | 2012-03-06 14:25 Resource Binding for Datapaths with Improved Post-Silicon Skew Tunability Yosuke Haruta, Mineo Kaneko (JAIST)  VLD2011-127 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | With the progress of fabrication-process technology, the variation of signal transmission delay due to variations in process parameters becomes larger, and the yield degradation due to timing errors comes to be a serious problem in recent large scale integration (LSI).To overcome this problem, various pre-silicon and post-silicon approaches have been proposed.Here we focus on clock skew tuning (post-silicon skew tuning) and we propose a new resource binding in high level synthesis for a datapath with maximized skew tuning success rate i.e., the probability of success in timing-skew tuning through embedded programable delay elements.Our proposed algorithm named parallel left edge guarantees the minimum (or the specified) number of resource while the decisions made during resource binding are based on the evaluation of the skew tuning success rate.The experimental results show us the importance of decision making based on the exact evaluation of skew tuning success rate, but they also show the poor ability of our parallel left edge in finding globally better solutions. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Timing-adjustability / resource binding / high level synthesis / delay variation / programable delay element / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 111, no. 450, VLD2011-127, pp. 43-48, March 2012. | |
| Paper # | VLD2011-127 | |
| Date of Issue | 2012-02-28 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2011-127 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2012-03-06 - 2012-03-07 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | B-con Plaza |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Methodologies for System-on-a-chip |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2012-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Resource Binding for Datapaths with Improved Post-Silicon Skew Tunability |
| Sub Title (in English) | |
| Keyword(1) | Timing-adjustability |
| Keyword(2) | resource binding |
| Keyword(3) | high level synthesis |
| Keyword(4) | delay variation |
| Keyword(5) | programable delay element |
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| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Yosuke Haruta |
| 1st Author's Affiliation | Japan Advanced Institute of Science and Technology (JAIST) |
| 2nd Author's Name | Mineo Kaneko |
| 2nd Author's Affiliation | Japan Advanced Institute of Science and Technology (JAIST) |
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| Speaker | Author-1 |
| Date Time | 2012-03-06 14:25:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2011-127 |
| Volume (vol) | vol.111 |
| Number (no) | no.450 |
| Page | pp.43-48 |
| #Pages | 6 |
| Date of Issue | 2012-02-28 (VLD) |
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