Paper Abstract and Keywords |
Presentation |
2012-04-24 14:50
Device-Conscious Circuit Designs for 0.5-V High-Speed Nanoscale CMOS LSIs Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya (Hitachi), Masashi Horiguchi (Renesas) ICD2012-15 Link to ES Tech. Rep. Archives: ICD2012-15 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The feasibility of 0.5-V memory-rich nanoscale CMOS LSIs was studied. First, nanoscale fully-depleted MOSFETs (FD MOS) and repair techniques are discussed in terms of Vt-variation. Second, dual-VDD dual-Vt logic circuits and a boosted word-voltage scheme for a 0.5-V 6-T SRAM are proposed and evaluated by simulation with a 25-nm planar FD MOS. Third, the importance of using compensation circuits for process, voltage, and temperature variations is stressed. Finally, it is concluded that a 0.5-V memory-rich CMOS LSI is possible while reducing the power to one-eighth that of a conventional 1-V CMOS LSI if the above devices and circuits are used. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
SRAM / Logic Circuit / SOTB / FinFET / Threshold Voltage Variability / / / |
Reference Info. |
IEICE Tech. Rep., vol. 112, no. 15, ICD2012-15, pp. 79-84, April 2012. |
Paper # |
ICD2012-15 |
Date of Issue |
2012-04-16 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
ICD2012-15 Link to ES Tech. Rep. Archives: ICD2012-15 |
Conference Information |
Committee |
ICD |
Conference Date |
2012-04-23 - 2012-04-24 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Seion-so, Tsunagi Hot Spring (Iwate) |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Memory Device Technologies |
Paper Information |
Registration To |
ICD |
Conference Code |
2012-04-ICD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Device-Conscious Circuit Designs for 0.5-V High-Speed Nanoscale CMOS LSIs |
Sub Title (in English) |
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Keyword(1) |
SRAM |
Keyword(2) |
Logic Circuit |
Keyword(3) |
SOTB |
Keyword(4) |
FinFET |
Keyword(5) |
Threshold Voltage Variability |
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1st Author's Name |
Akira Kotabe |
1st Author's Affiliation |
Central Research Laboratory, Hitachi, Ltd. (Hitachi) |
2nd Author's Name |
Kiyoo Itoh |
2nd Author's Affiliation |
Central Research Laboratory, Hitachi, Ltd. (Hitachi) |
3rd Author's Name |
Riichiro Takemura |
3rd Author's Affiliation |
Central Research Laboratory, Hitachi, Ltd. (Hitachi) |
4th Author's Name |
Ryuta Tsuchiya |
4th Author's Affiliation |
Central Research Laboratory, Hitachi, Ltd. (Hitachi) |
5th Author's Name |
Masashi Horiguchi |
5th Author's Affiliation |
Renesas Electronics Corporation (Renesas) |
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Speaker |
Author-1 |
Date Time |
2012-04-24 14:50:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
ICD2012-15 |
Volume (vol) |
vol.112 |
Number (no) |
no.15 |
Page |
pp.79-84 |
#Pages |
6 |
Date of Issue |
2012-04-16 (ICD) |
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