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| Presentation | 2012-05-29 16:45 Implementation and evaluation of the AES/ADPCM on STP and FPGA with Behavioral Synthesis Yukihito Ishida, Seiya Shibata, Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ)  RECONF2012-14 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Reconfigurable techniques are attracting attention as an alternative to dedicated hardware of SoC. We have evaluated FPGA and STP engine in order to confirm their performance whether they can substitute the dedicated hardware of SoC. We selected AES and ADPCM applications to compare the performance of FPGA and STP engine. The applications were synthesized with the same behavioral synthesis tools. Then, we implemented them onto FPGA and STP engine using the integrated development environments. For the evaluation, we compared them in terms of hardware area, the number of states, the number of cycles, frequency, and execution time. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | behavioral synthesis / dynamically reconfigurable system / FPGA / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 112, no. 70, RECONF2012-14, pp. 77-82, May 2012. | |
| Paper # | RECONF2012-14 | |
| Date of Issue | 2012-05-22 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Notes on Review | This article is a technical report without peer review, and its polished version will be published elsewhere. | |
| Download PDF | RECONF2012-14 |
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| Conference Information | |
| Committee | RECONF |
| Conference Date | 2012-05-29 - 2012-05-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Tiruru (Naha Okinawa, Japan) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable Systems, etc. |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2012-05-RECONF |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation and evaluation of the AES/ADPCM on STP and FPGA with Behavioral Synthesis |
| Sub Title (in English) | |
| Keyword(1) | behavioral synthesis |
| Keyword(2) | dynamically reconfigurable system |
| Keyword(3) | FPGA |
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| 1st Author's Name | Yukihito Ishida |
| 1st Author's Affiliation | Nagoya University (Nagoya Univ) |
| 2nd Author's Name | Seiya Shibata |
| 2nd Author's Affiliation | Nagoya University (Nagoya Univ) |
| 3rd Author's Name | Yuki Ando |
| 3rd Author's Affiliation | Nagoya University (Nagoya Univ) |
| 4th Author's Name | Shinya Honda |
| 4th Author's Affiliation | Nagoya University (Nagoya Univ) |
| 5th Author's Name | Hiroaki Takada |
| 5th Author's Affiliation | Nagoya University (Nagoya Univ) |
| 6th Author's Name | Masato Edahiro |
| 6th Author's Affiliation | Nagoya University (Nagoya Univ) |
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| Speaker | Author-1 |
| Date Time | 2012-05-29 16:45:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2012-14 |
| Volume (vol) | vol.112 |
| Number (no) | no.70 |
| Page | pp.77-82 |
| #Pages | 6 |
| Date of Issue | 2012-05-22 (RECONF) |
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