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Paper Abstract and Keywords
Presentation 2012-05-30 14:55
Multiple supply voltages aware high-speed and high-efficient high-level synthesis for HDR architectures
Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2012-2
Abstract (in Japanese) (See Japanese page) 
(in English) HDR architecture has been proposed as a platform that integrates energy-efficiency and interconnection delays into high-level synthesis. In this paper, we propose new multiple-supply-voltages aware high-speed and highefficiency high-level synthesis for HDR architectures. We propose two new techniques, “virtual area estimation” and “floorplanning directed huddling”, and integrate them into an HDR architecture synthesis algorithm. “Virtual area estimation” reduces huddles’ area oscillating during iterations, which impedes convergence of conventional methods. “Floorplanning directed huddling” determines huddle structure effectively by resolving floorplanning and functional unit assignment inside huddles at the same time. Experimental results show that our algorithm achieves about 40% run-time-saving compared with the conventional methods.
Keyword (in Japanese) (See Japanese page) 
(in English) high-level synthesis / energy-efficient / low-power / interconnection delay / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 71, VLD2012-2, pp. 7-12, May 2012.
Paper # VLD2012-2 
Date of Issue 2012-05-23 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2012-2

Conference Information
Committee IPSJ-SLDM VLD  
Conference Date 2012-05-30 - 2012-05-31 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Design, etc. 
Paper Information
Registration To VLD 
Conference Code 2012-05-SLDM-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Multiple supply voltages aware high-speed and high-efficient high-level synthesis for HDR architectures 
Sub Title (in English)  
Keyword(1) high-level synthesis  
Keyword(2) energy-efficient  
Keyword(3) low-power  
Keyword(4) interconnection delay  
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1st Author's Name Shin-ya Abe  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Masao Yanagisawa  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Nozomu Togawa  
3rd Author's Affiliation Waseda University (Waseda Univ.)
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Speaker Author-1 
Date Time 2012-05-30 14:55:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2012-2 
Volume (vol) vol.112 
Number (no) no.71 
Page pp.7-12 
#Pages 6 
Date of Issue 2012-05-23 (VLD) 

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