Paper Abstract and Keywords |
Presentation |
2012-06-22 15:45
An Evaluation of Low Power BIST Method Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara (Kyutech) DC2012-14 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Low-power test technology has been investigated deeply to achieve an accurate and efficient testing. Although many sophisticated methods are proposed for scan-test, there are not so many for logic BIST because of its uncontrollable randomness. However, logic BIST currently becomes vital for system debug or field test. This paper proposes a novel low power BIST technology that eliminates the specified high-frequency parts of vectors in scan-shift and also reduces capture power. The authors show that the proposed technology not only reduces test power but also controls test power with little loss of test coverage. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Logic BIST / Test power / Fault coverage / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 112, no. 102, DC2012-14, pp. 33-38, June 2012. |
Paper # |
DC2012-14 |
Date of Issue |
2012-06-15 (DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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DC2012-14 |
Conference Information |
Committee |
DC |
Conference Date |
2012-06-22 - 2012-06-22 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Room B3-1 Kikai-Shinko-Kaikan Bldg |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design, Test, Verification |
Paper Information |
Registration To |
DC |
Conference Code |
2012-06-DC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
An Evaluation of Low Power BIST Method |
Sub Title (in English) |
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Keyword(1) |
Logic BIST |
Keyword(2) |
Test power |
Keyword(3) |
Fault coverage |
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1st Author's Name |
Yasuo Sato |
1st Author's Affiliation |
Kyushu Institute of Technology (Kyutech) |
2nd Author's Name |
Senling Wang |
2nd Author's Affiliation |
Kyushu Institute of Technology (Kyutech) |
3rd Author's Name |
Takaaki Kato |
3rd Author's Affiliation |
Kyushu Institute of Technology (Kyutech) |
4th Author's Name |
Kohei Miyase |
4th Author's Affiliation |
Kyushu Institute of Technology (Kyutech) |
5th Author's Name |
Seiji Kajihara |
5th Author's Affiliation |
Kyushu Institute of Technology (Kyutech) |
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Speaker |
Author-1 |
Date Time |
2012-06-22 15:45:00 |
Presentation Time |
25 minutes |
Registration for |
DC |
Paper # |
DC2012-14 |
Volume (vol) |
vol.112 |
Number (no) |
no.102 |
Page |
pp.33-38 |
#Pages |
6 |
Date of Issue |
2012-06-15 (DC) |
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