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Paper Abstract and Keywords
Presentation 2012-07-19 11:35
Design of a 2bit Bit-Slice Half-Precision Floating-Point Multiplier Using SFQ Circuits
Yohei Naruse (Kyoto Univ.), Nobutaka Kito (Chukyo Univ.), Naofumi Takagi (Kyoto Univ.) SCE2012-12
Abstract (in Japanese) (See Japanese page) 
(in English) Single flux quantum (SFQ) circuits are expected as next-generation circuits.
Arithmetic circuits using SFQ circuits have been designed based on bit-serial structure.
When the bit width of input data increases, the number of cycles for input data increases.
In this report, we propose a floating-point multiplier operating based on bit-slice architecture.
We design a 2bit bit-slice floating-point multiplier and bit-serial floating-point multiplier at gate level and
conpare the performances of them respectively.
We design a 2bit bit-slice half-precision floating-point multiplier.
The number of junctions and delay time are 50531 and 7849ps.
Keyword (in Japanese) (See Japanese page) 
(in English) SFQ circuit / Single Flux Quantum circuit / multiplier / bit-slice / floating-point multiplier / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 138, SCE2012-12, pp. 19-23, July 2012.
Paper # SCE2012-12 
Date of Issue 2012-07-12 (SCE) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SCE2012-12

Conference Information
Committee SCE  
Conference Date 2012-07-19 - 2012-07-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Signal processing technologies and their applications, etc. 
Paper Information
Registration To SCE 
Conference Code 2012-07-SCE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design of a 2bit Bit-Slice Half-Precision Floating-Point Multiplier Using SFQ Circuits 
Sub Title (in English)  
Keyword(1) SFQ circuit  
Keyword(2) Single Flux Quantum circuit  
Keyword(3) multiplier  
Keyword(4) bit-slice  
Keyword(5) floating-point multiplier  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Yohei Naruse  
1st Author's Affiliation Kyoto University (Kyoto Univ.)
2nd Author's Name Nobutaka Kito  
2nd Author's Affiliation Chukyo University (Chukyo Univ.)
3rd Author's Name Naofumi Takagi  
3rd Author's Affiliation Kyoto University (Kyoto Univ.)
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Speaker Author-1 
Date Time 2012-07-19 11:35:00 
Presentation Time 25 minutes 
Registration for SCE 
Paper # SCE2012-12 
Volume (vol) vol.112 
Number (no) no.138 
Page pp.19-23 
#Pages 5 
Date of Issue 2012-07-12 (SCE) 

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