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Paper Abstract and Keywords
Presentation 2012-08-03 16:20
A 40nm Ultra Low Voltage SAR ADC with Timing Optimized Asynchronous Clock Generator
Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro (Keio Univ.) SDM2012-88 ICD2012-56
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents an ultra low power and low voltage successive approximation register (SAR) analog to digital converter (ADC) that uses an adaptive timing optimized asynchronous clock generator. By calibrating the delay time of the clock generator, the DAC settling time is optimized to counter the device mismatch. Test chip has been fabricated in 40nm standard CMOS process and achieved 7.5-ENOB (Effective Number of Bits) and figure of merit (FoM) of 8.75-fJ/conversion-step with 2.048MS/s.
Keyword (in Japanese) (See Japanese page) 
(in English) ultra low voltage / ultra low power / SAR / ADC / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 170, ICD2012-56, pp. 139-144, Aug. 2012.
Paper # ICD2012-56 
Date of Issue 2012-07-26 (SDM, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2012-88 ICD2012-56

Conference Information
Committee ICD SDM  
Conference Date 2012-08-02 - 2012-08-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Sapporo Center for Gender Equality, Sapporo, Hokkaido 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Low-power, low-voltage device and circuit technology 
Paper Information
Registration To ICD 
Conference Code 2012-08-ICD-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A 40nm Ultra Low Voltage SAR ADC with Timing Optimized Asynchronous Clock Generator 
Sub Title (in English)  
Keyword(1) ultra low voltage  
Keyword(2) ultra low power  
Keyword(3) SAR  
Keyword(4) ADC  
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1st Author's Name Ryota Sekimoto  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Akira Shikata  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Kentaro Yoshioka  
3rd Author's Affiliation Keio University (Keio Univ.)
4th Author's Name Tadahiro Kuroda  
4th Author's Affiliation Keio University (Keio Univ.)
5th Author's Name Hiroki Ishikuro  
5th Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2012-08-03 16:20:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # SDM2012-88, ICD2012-56 
Volume (vol) vol.112 
Number (no) no.169(SDM), no.170(ICD) 
Page pp.139-144 
#Pages 6 
Date of Issue 2012-07-26 (SDM, ICD) 

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