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Paper Abstract and Keywords
Presentation 2012-09-28 09:10
Development of Generalized Encoder of BCH Code for Embedded System
Nagamasa Mizushima, Yukihiro Takatani, Junji Ogawa, Atsushi Ishikawa (Hitachi) IT2012-36
Abstract (in Japanese) (See Japanese page) 
(in English) For embedded systems that write data into flash memories at high speed, a parity of BCH code used for error correcting of the data is generated by a dedicated circuit included in their controllers. However, error features of flash memories differ depending on vendors or generations. Therefore, the circuit should support various code lengths and correctable error bits. We developed the generalized encoder of BCH code based on an architecture where coefficient bit-strings of both generator and parity polynomials stored in external RAM are input to or output from a pipeline typed sum-product operator. This architecture is able to support arbitrary-degree generator polynomials in response to the RAM capacity like never before, and makes it easier to design high-speed encoder than ever before.
Keyword (in Japanese) (See Japanese page) 
(in English) Flash memory / ECC / BCH code / Logic circuit / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 215, IT2012-36, pp. 31-36, Sept. 2012.
Paper # IT2012-36 
Date of Issue 2012-09-20 (IT) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF IT2012-36

Conference Information
Committee IT  
Conference Date 2012-09-27 - 2012-09-28 
Place (in Japanese) (See Japanese page) 
Place (in English) Kusatsu Seminar House 
Topics (in Japanese) (See Japanese page) 
Topics (in English) error correcting codes, general 
Paper Information
Registration To IT 
Conference Code 2012-09-IT 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Development of Generalized Encoder of BCH Code for Embedded System 
Sub Title (in English)  
Keyword(1) Flash memory  
Keyword(2) ECC  
Keyword(3) BCH code  
Keyword(4) Logic circuit  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Nagamasa Mizushima  
1st Author's Affiliation Hitachi, Ltd. Yokohama Research Laboratory (Hitachi)
2nd Author's Name Yukihiro Takatani  
2nd Author's Affiliation Hitachi, Ltd. Yokohama Research Laboratory (Hitachi)
3rd Author's Name Junji Ogawa  
3rd Author's Affiliation Hitachi, Ltd. Yokohama Research Laboratory (Hitachi)
4th Author's Name Atsushi Ishikawa  
4th Author's Affiliation Hitachi, Ltd. Information & Telecommunication Systems Company (Hitachi)
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Speaker Author-1 
Date Time 2012-09-28 09:10:00 
Presentation Time 25 minutes 
Registration for IT 
Paper # IT2012-36 
Volume (vol) vol.112 
Number (no) no.215 
Page pp.31-36 
#Pages 6 
Date of Issue 2012-09-20 (IT) 

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