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Paper Abstract and Keywords
Presentation 2012-11-27 10:55
An FPGA Implementation of Reconfigurable Real-Time Vision Architecture
Jorge Hiraiwa, Hideharu Amano (Keio Univ.) CPSY2012-54
Abstract (in Japanese) (See Japanese page) 
(in English) A video processing architecture based on FPGA for real-time embedded vision systems is proposed in this paper. Recently, embedded vision systems are used in various applications. On the other hand,
the throughput required to the system has been increasing as the high-definition vision replaces the current vision systems. Since more complex vision algorithms become available, higher performance and better expandability are requested accordingly. As a solution for this challenging situation, FPGA is now focused as an embedded vision system platform. In addition, high-level synthesis design method are prefered instead of traditional low-level design based on hardware description languages with lower productivity. In this study, we implemented a video processing pipelined architecture that offers flexibility for interchange processing modules. Each module was implemented using Verilog-HDL and Vivado HLS for its evaluation.
Keyword (in Japanese) (See Japanese page) 
(in English) Real-Time Vision Architecture / FPGA / High Level Synthesis / / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 322, CPSY2012-54, pp. 39-44, Nov. 2012.
Paper # CPSY2012-54 
Date of Issue 2012-11-19 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2012-54

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2012-11-26 - 2012-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) Centennial Hall Kyushu University School of Medicine 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2012 -New Field of VLSI Design- 
Paper Information
Registration To CPSY 
Conference Code 2012-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An FPGA Implementation of Reconfigurable Real-Time Vision Architecture 
Sub Title (in English)  
Keyword(1) Real-Time Vision Architecture  
Keyword(2) FPGA  
Keyword(3) High Level Synthesis  
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1st Author's Name Jorge Hiraiwa  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Hideharu Amano  
2nd Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2012-11-27 10:55:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2012-54 
Volume (vol) vol.112 
Number (no) no.322 
Page pp.39-44 
#Pages 6 
Date of Issue 2012-11-19 (CPSY) 

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