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Paper Abstract and Keywords
Presentation 2012-11-28 14:55
A Scan-Out Power Reduction Method for Multi-Cycle BIST
Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase (Kyutech) VLD2012-102 DC2012-68
Abstract (in Japanese) (See Japanese page) 
(in English) Excessive power dissipation in logic BIST is a serious problem. Although many low power BIST approaches that focus on scan-in power or capture power have been proposed, there are not so many techniques for scan-out power reduction due to the difficulty in controlling the captured test responses. In this paper, we propose a novel scan-out power reduction method for multi-cycle BIST that directly reduces scan-out power by modifying some flip-flops’ values in scan chains at the last capture, and without sacrificing the test coverage.
Keyword (in Japanese) (See Japanese page) 
(in English) low power / BIST / multi-cycle test / shift power / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 320, VLD2012-102, pp. 249-254, Nov. 2012.
Paper # VLD2012-102 
Date of Issue 2012-11-19 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2012-102 DC2012-68

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2012-11-26 - 2012-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) Centennial Hall Kyushu University School of Medicine 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2012 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2012-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Scan-Out Power Reduction Method for Multi-Cycle BIST 
Sub Title (in English)  
Keyword(1) low power  
Keyword(2) BIST  
Keyword(3) multi-cycle test  
Keyword(4) shift power  
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1st Author's Name Senling Wang  
1st Author's Affiliation Kyushu Institute of Technology (Kyutech)
2nd Author's Name Yasuo Sato  
2nd Author's Affiliation Kyushu Institute of Technology (Kyutech)
3rd Author's Name Seiji Kajihara  
3rd Author's Affiliation Kyushu Institute of Technology (Kyutech)
4th Author's Name Kohei Miyase  
4th Author's Affiliation Kyushu Institute of Technology (Kyutech)
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Speaker Author-1 
Date Time 2012-11-28 14:55:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2012-102, DC2012-68 
Volume (vol) vol.112 
Number (no) no.320(VLD), no.321(DC) 
Page pp.249-254 
#Pages 6 
Date of Issue 2012-11-19 (VLD, DC) 

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