Paper Abstract and Keywords |
Presentation |
2012-12-17 15:55
[Poster Presentation]
A Design of Patch Clamp Measurement System using 0.18μm CMOS Technology Wataru Nakayama, Ryuich Ohno, Yohei Yasuda, Takuya Kawashima, Nobuhiko Nakano (Keio Univ.) ICD2012-110 Link to ES Tech. Rep. Archives: ICD2012-110 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The Patch Clamp, which can measure ion-channel current of membrane, is one of the way to analyze the neuron and its measurement system is required to be minimized. We designed LSI Measurement system for Patch Clamp using 0.18$\mu$m CMOS process. This system includes following block ; I-V Converter for converting current to voltage , ${\rm R_s}$ compensation system for compensating pipette-cell parasitic serial resistance , and ${\rm C_p}$ compensation system for compensating pipette parasitic capasitance. Capacitance Compensation system can compensate up to 70pF.When ${\rm R_s}$ is 20MΩ,the freaquency range of input Voltage ${\rm V}_{CMD}$ is limited to1.41kHz cause of the parasitics. Resistance Compensation system expanded its freaquency range up to 2.35kHz. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Patch-Clamp / Resistance-Compensation / Capacitance-Compensation / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 112, no. 365, ICD2012-110, pp. 73-76, Dec. 2012. |
Paper # |
ICD2012-110 |
Date of Issue |
2012-12-10 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
ICD2012-110 Link to ES Tech. Rep. Archives: ICD2012-110 |
Conference Information |
Committee |
ICD |
Conference Date |
2012-12-17 - 2012-12-18 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Tokyo Tech Front |
Topics (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
ICD |
Conference Code |
2012-12-ICD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Design of Patch Clamp Measurement System using 0.18μm CMOS Technology |
Sub Title (in English) |
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Keyword(1) |
Patch-Clamp |
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Resistance-Compensation |
Keyword(3) |
Capacitance-Compensation |
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1st Author's Name |
Wataru Nakayama |
1st Author's Affiliation |
Keio University (Keio Univ.) |
2nd Author's Name |
Ryuich Ohno |
2nd Author's Affiliation |
Keio University (Keio Univ.) |
3rd Author's Name |
Yohei Yasuda |
3rd Author's Affiliation |
Keio University (Keio Univ.) |
4th Author's Name |
Takuya Kawashima |
4th Author's Affiliation |
Keio University (Keio Univ.) |
5th Author's Name |
Nobuhiko Nakano |
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Keio University (Keio Univ.) |
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Speaker |
Author-1 |
Date Time |
2012-12-17 15:55:00 |
Presentation Time |
120 minutes |
Registration for |
ICD |
Paper # |
ICD2012-110 |
Volume (vol) |
vol.112 |
Number (no) |
no.365 |
Page |
pp.73-76 |
#Pages |
4 |
Date of Issue |
2012-12-10 (ICD) |
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