Paper Abstract and Keywords |
Presentation |
2013-01-16 16:00
Break Even Time Evaluation of Run-Time Power Gating Control by On-chip Leakage Monitor Kensaku Matsunaga, Masaru Kudo (SIT), Yuya Ohta, Nao Konishi (SIT), Hideharu Amano (KU), Ryuichi Sakamoto, Mitaro Namiki (TUAT), Kimiyoshi Usami (SIT) VLD2012-118 CPSY2012-67 RECONF2012-72 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Run-time Power Gating (RTPG) reduces leakage energy by turning off a power switch(PS) for idle periods of a circuit during the operation. To get energy savings in RTPG, power gating needs to be enabled only when the idle time exceeds the break-even time (BET) at which leakage energy reduction by turning off PS becomes equal to the energy overhead. Since BET changes with leakage current,on-line detection of BET is required for RTPG controls. We implemented an on-chip leakage monitor in 65nm CMOS technology, and showed the relation between BET of each computing unit , and leakage current. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
On-chip Leakage monitor / Run-time Power Gating / Break Even Time / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 112, no. 375, VLD2012-118, pp. 63-68, Jan. 2013. |
Paper # |
VLD2012-118 |
Date of Issue |
2013-01-09 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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VLD2012-118 CPSY2012-67 RECONF2012-72 |
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