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Paper Abstract and Keywords
Presentation 2013-01-16 16:00
Break Even Time Evaluation of Run-Time Power Gating Control by On-chip Leakage Monitor
Kensaku Matsunaga, Masaru Kudo (SIT), Yuya Ohta, Nao Konishi (SIT), Hideharu Amano (KU), Ryuichi Sakamoto, Mitaro Namiki (TUAT), Kimiyoshi Usami (SIT) VLD2012-118 CPSY2012-67 RECONF2012-72
Abstract (in Japanese) (See Japanese page) 
(in English) Run-time Power Gating (RTPG) reduces leakage energy by turning off a power switch(PS) for idle periods of a circuit during the operation. To get energy savings in RTPG, power gating needs to be enabled only when the idle time exceeds the break-even time (BET) at which leakage energy reduction by turning off PS becomes equal to the energy overhead. Since BET changes with leakage current,on-line detection of BET is required for RTPG controls. We implemented an on-chip leakage monitor in 65nm CMOS technology, and showed the relation between BET of each computing unit , and leakage current.
Keyword (in Japanese) (See Japanese page) 
(in English) On-chip Leakage monitor / Run-time Power Gating / Break Even Time / / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 375, VLD2012-118, pp. 63-68, Jan. 2013.
Paper # VLD2012-118 
Date of Issue 2013-01-09 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2012-118 CPSY2012-67 RECONF2012-72

Conference Information
Committee CPSY VLD RECONF IPSJ-SLDM  
Conference Date 2013-01-16 - 2013-01-17 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2013-01-CPSY-VLD-RECONF-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Break Even Time Evaluation of Run-Time Power Gating Control by On-chip Leakage Monitor 
Sub Title (in English)  
Keyword(1) On-chip Leakage monitor  
Keyword(2) Run-time Power Gating  
Keyword(3) Break Even Time  
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1st Author's Name Kensaku Matsunaga  
1st Author's Affiliation Shibaura Institute of Technology (SIT)
2nd Author's Name Masaru Kudo  
2nd Author's Affiliation Shibaura Institute of Technology (SIT)
3rd Author's Name Yuya Ohta  
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4th Author's Name Nao Konishi  
4th Author's Affiliation Shibaura Institute of Technology (SIT)
5th Author's Name Hideharu Amano  
5th Author's Affiliation Keio University (KU)
6th Author's Name Ryuichi Sakamoto  
6th Author's Affiliation Tokyo University Of Agriculture and Technology (TUAT)
7th Author's Name Mitaro Namiki  
7th Author's Affiliation Tokyo University Of Agriculture and Technology (TUAT)
8th Author's Name Kimiyoshi Usami  
8th Author's Affiliation Shibaura Insutitute of Technology (SIT)
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Speaker Author-1 
Date Time 2013-01-16 16:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2012-118, CPSY2012-67, RECONF2012-72 
Volume (vol) vol.112 
Number (no) no.375(VLD), no.376(CPSY), no.377(RECONF) 
Page pp.63-68 
#Pages 6 
Date of Issue 2013-01-09 (VLD, CPSY, RECONF) 

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