Paper Abstract and Keywords |
Presentation |
2013-01-17 14:50
Implementation of 3-D stencil computation with an FPGA accelerator and a high level synthesis tool Yoshihiro Nakamura, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) VLD2012-133 CPSY2012-82 RECONF2012-87 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this paper, we implemented a stencil computation kernel on an FPGA accelerator using MaxCompiler and MaxGenFD tools, which are a high-level synthesis compiler and its upper-layer framework. The performance evaluation results showed that an optimized system with one FPGA chip calculated 1.5e+09 grids per second, which is 21.29 and 5.08 times faster than baseline implementation and optimized CPU implementation, respectively. We also proposed and evaluated a performance estimation method for FPGA-based stencil computation. The difference between the estimated and measured performance was increased when the pipeline frequency of stencil computation was high, suggesting the pipeline stalls occurred due to the lack of data transfer throughput. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA / acceleration / high-level synthesis / stencil computation / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 112, no. 377, RECONF2012-87, pp. 153-158, Jan. 2013. |
Paper # |
RECONF2012-87 |
Date of Issue |
2013-01-09 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2012-133 CPSY2012-82 RECONF2012-87 |
Conference Information |
Committee |
CPSY VLD RECONF IPSJ-SLDM |
Conference Date |
2013-01-16 - 2013-01-17 |
Place (in Japanese) |
(See Japanese page) |
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(See Japanese page) |
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Paper Information |
Registration To |
RECONF |
Conference Code |
2013-01-CPSY-VLD-RECONF-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Implementation of 3-D stencil computation with an FPGA accelerator and a high level synthesis tool |
Sub Title (in English) |
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Keyword(1) |
FPGA |
Keyword(2) |
acceleration |
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high-level synthesis |
Keyword(4) |
stencil computation |
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1st Author's Name |
Yoshihiro Nakamura |
1st Author's Affiliation |
Nagasaki University (Nagasaki Univ.) |
2nd Author's Name |
Keisuke Dohi |
2nd Author's Affiliation |
Nagasaki University (Nagasaki Univ.) |
3rd Author's Name |
Yuichiro Shibata |
3rd Author's Affiliation |
Nagasaki University (Nagasaki Univ.) |
4th Author's Name |
Kiyoshi Oguri |
4th Author's Affiliation |
Nagasaki University (Nagasaki Univ.) |
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Speaker |
Author-1 |
Date Time |
2013-01-17 14:50:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
VLD2012-133, CPSY2012-82, RECONF2012-87 |
Volume (vol) |
vol.112 |
Number (no) |
no.375(VLD), no.376(CPSY), no.377(RECONF) |
Page |
pp.153-158 |
#Pages |
6 |
Date of Issue |
2013-01-09 (VLD, CPSY, RECONF) |
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