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Paper Abstract and Keywords
Presentation 2013-01-31 10:45
A study on a FPGA implementation of real time foreground segmentation
Tomohito Kajimoto, Ryo Yagi, Takao Nishitani (Tokyo Metropolitan Univ.) SIP2012-83 RCS2012-240
Abstract (in Japanese) (See Japanese page) 
(in English) A prototype processor based on the multi-resolution GMM Foreground Segmentation algorithm by using Walsh Transform domain is implemented by a FPGA chip. The spatial processing of the Walsh transform is realized by using a tightly coupled programmable multi-processor and the temporal processing of GMM Foreground Segmentation is realized by using a
multi-thread programmable processor. In this paper, a tightly coupled Walsh transform feature generation processing is described which employs a streaming processing approach. The implemented processor can achieve real time processing of an HDTV video sequence of 30fps by 100MHz clocks.
Keyword (in Japanese) (See Japanese page) 
(in English) Walsh Transform / Foreground Segmentation / FPGA / IP-CORE / Programmable Processor / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 423, SIP2012-83, pp. 13-18, Jan. 2013.
Paper # SIP2012-83 
Date of Issue 2013-01-24 (SIP, RCS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SIP2012-83 RCS2012-240

Conference Information
Committee SIP RCS  
Conference Date 2013-01-31 - 2013-02-01 
Place (in Japanese) (See Japanese page) 
Place (in English) Viewport-Kure-Hotel (Kure) 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SIP 
Conference Code 2013-01-SIP-RCS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A study on a FPGA implementation of real time foreground segmentation 
Sub Title (in English)  
Keyword(1) Walsh Transform  
Keyword(2) Foreground Segmentation  
Keyword(3) FPGA  
Keyword(4) IP-CORE  
Keyword(5) Programmable Processor  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Tomohito Kajimoto  
1st Author's Affiliation Tokyo Metropolitan University (Tokyo Metropolitan Univ.)
2nd Author's Name Ryo Yagi  
2nd Author's Affiliation Tokyo Metropolitan University (Tokyo Metropolitan Univ.)
3rd Author's Name Takao Nishitani  
3rd Author's Affiliation Tokyo Metropolitan University (Tokyo Metropolitan Univ.)
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Speaker Author-1 
Date Time 2013-01-31 10:45:00 
Presentation Time 25 minutes 
Registration for SIP 
Paper # SIP2012-83, RCS2012-240 
Volume (vol) vol.112 
Number (no) no.423(SIP), no.424(RCS) 
Page pp.13-18 
#Pages 6 
Date of Issue 2013-01-24 (SIP, RCS) 

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