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| Presentation | 2013-03-06 13:40 A Delay Control Circuit with Channel Length Decomposition and Its Application Yuichi Toyota, Yuki Nakashima, Toru Fujimura, Shigetoshi Nakatake (Univ of Kitakyushu)  VLD2012-158 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In recent years, as the progress of the semiconductor manufacturing, the variations of circuit performance due to device variations at the manufacturing has become more remarkable. Hence, the delay elements for synchronizing the signal has been employed in microprocessors, memory circuits, PLL (Phase Locked Loop), DLL, (Delay Locked Loop), etc. Especially, PDE (Programmable Delay Elements) is focused which can tune the delay after the manufacturing. In this paper, we propose a novel PDE circuit based on a channel length decomposition techniques of a MOS transistor. The proposed circuit provides not only a good linearity of the delay tuning but also a large reduction of dynamic power consumption. Besides, we propose a coarse grain-oriented digital PLL as an example of the application of the PDE, and report the power reduction of our PLL compared with the existing PLL. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Programmable Delay Eelements / Channel Length Decomposition / Phase Locked Loop / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 112, no. 451, VLD2012-158, pp. 123-128, March 2013. | |
| Paper # | VLD2012-158 | |
| Date of Issue | 2013-02-25 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2012-158 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2013-03-04 - 2013-03-06 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2013-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Delay Control Circuit with Channel Length Decomposition and Its Application |
| Sub Title (in English) | |
| Keyword(1) | Programmable Delay Eelements |
| Keyword(2) | Channel Length Decomposition |
| Keyword(3) | Phase Locked Loop |
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| Keyword(8) | |
| 1st Author's Name | Yuichi Toyota |
| 1st Author's Affiliation | University of Kitakyushu (Univ of Kitakyushu) |
| 2nd Author's Name | Yuki Nakashima |
| 2nd Author's Affiliation | University of Kitakyushu (Univ of Kitakyushu) |
| 3rd Author's Name | Toru Fujimura |
| 3rd Author's Affiliation | University of Kitakyushu (Univ of Kitakyushu) |
| 4th Author's Name | Shigetoshi Nakatake |
| 4th Author's Affiliation | University of Kitakyushu (Univ of Kitakyushu) |
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| Speaker | Author-1 |
| Date Time | 2013-03-06 13:40:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2012-158 |
| Volume (vol) | vol.112 |
| Number (no) | no.451 |
| Page | pp.123-128 |
| #Pages | 6 |
| Date of Issue | 2013-02-25 (VLD) |
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