| Paper Abstract and Keywords |
| Presentation |
2013-04-12 14:20
[Invited Lecture]
A Power-Reduction Scheme for Dual-Power-Supply SRAM Using BL Power Calculator and Digital LDO Miyako Shizuno, Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Sinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa (Toshiba) ICD2013-19 |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
This paper presents a dual-power-supply SRAM that reduces active and stand-by power from room temperature (RT) to high temperature (HT) using a BL power calculator (BLPC) and a digitally controllable retention circuit (DCRC). A test-chip is fabricated in a 28nm CMOS technology with a 0.120μm2 6T-SRAM cell. With these schemes, active and standby power consumptions at 25°C are reduced by 27% and 85%, respectively. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
A Dual-power supply SRAM / Power reduction / BL power calculator / Digital LDO / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 113, no. 1, ICD2013-19, pp. 97-102, April 2013. |
| Paper # |
ICD2013-19 |
| Date of Issue |
2013-04-04 (ICD) |
| ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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| Download PDF |
ICD2013-19 |