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Paper Abstract and Keywords
Presentation 2013-05-10 15:50
Comparison of Fixed Point and Floating Point Calculations for parallel processing of FDTD method using FPGA
Ryota Takasu, Tempei Hasegawa, Yoichi Tomioka (Tokyo Univ. of Agriculture and Tech.), Tsugumichi Shibata, Mamoru Nakanishi (NTT), Hitoshi Kitazawa (Tokyo Univ. of Agriculture and Tech.) EST2013-9
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we discuss the advantages and disadvantages of fixed point and floating point arithmetic calculations of different bit lengths for parallel processing of FDTD method using FPGA.
A processing element (PE) for a fixed point arithmetic calculation is comparable small, and it is suitable to implement more PEs while the precision is restricted.
On the other hand, a PE for a floating point arithmetic calculation can calculate with high accuracy while the number of mounted elements decreases.
We show the precision, processing speed estimation, and logic utilization for each PE, and select the optimal PE under given hardware resource and required precision.
Moreover, we show the comparison of parallel processing based on SIMD array of a proposed pipeline arithmetic unit with GPU.
Keyword (in Japanese) (See Japanese page) 
(in English) FDTD method / FPGA / Parallel processing / SIMD array / fixed and floating point / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 26, EST2013-9, pp. 45-50, May 2013.
Paper # EST2013-9 
Date of Issue 2013-05-03 (EST) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF EST2013-9

Conference Information
Committee EST  
Conference Date 2013-05-10 - 2013-05-10 
Place (in Japanese) (See Japanese page) 
Place (in English) NTT Science and Core Technology Laboratory Group 
Topics (in Japanese) (See Japanese page) 
Topics (in English) THz applications, Simulation technology, etc. 
Paper Information
Registration To EST 
Conference Code 2013-05-EST 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Comparison of Fixed Point and Floating Point Calculations for parallel processing of FDTD method using FPGA 
Sub Title (in English)  
Keyword(1) FDTD method  
Keyword(2) FPGA  
Keyword(3) Parallel processing  
Keyword(4) SIMD array  
Keyword(5) fixed and floating point  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Ryota Takasu  
1st Author's Affiliation Tokyo University of Agriculture and Technology (Tokyo Univ. of Agriculture and Tech.)
2nd Author's Name Tempei Hasegawa  
2nd Author's Affiliation Tokyo University of Agriculture and Technology (Tokyo Univ. of Agriculture and Tech.)
3rd Author's Name Yoichi Tomioka  
3rd Author's Affiliation Tokyo University of Agriculture and Technology (Tokyo Univ. of Agriculture and Tech.)
4th Author's Name Tsugumichi Shibata  
4th Author's Affiliation NTT Microsystem Integration Laboratories (NTT)
5th Author's Name Mamoru Nakanishi  
5th Author's Affiliation NTT Microsystem Integration Laboratories (NTT)
6th Author's Name Hitoshi Kitazawa  
6th Author's Affiliation Tokyo University of Agriculture and Technology (Tokyo Univ. of Agriculture and Tech.)
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Speaker Author-1 
Date Time 2013-05-10 15:50:00 
Presentation Time 25 minutes 
Registration for EST 
Paper # EST2013-9 
Volume (vol) vol.113 
Number (no) no.26 
Page pp.45-50 
#Pages 6 
Date of Issue 2013-05-03 (EST) 

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