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Paper Abstract and Keywords
Presentation 2013-05-16 16:25
SoC System Design Methodology with Fully-Coherent Cache
Kodai Moritaka (NAIST), Hiroaki Yoshida, Mitsuru Tomono (FLA), Yasuhiko Nakashima (NAIST) VLD2013-10
Abstract (in Japanese) (See Japanese page) 
(in English) As Chip Multi-Processors (CMPs) includes more processor cores in a single chip, the impact of its memory model on the entire performance, energy consumption and scalability is becoming dominant. Coherent cache model is used widely in such CMP systems because the programming for coherent cache model is easier than that
for streaming memory model.

On the other hand, every processing block (IP) in System-on-Chips (SoCs) has its own local memory such as scratchpad memory and local store and the communication between blocks is performed by Direct Memory Access (DMA). Thus, SoCs can be regarded as streaming memory model. As SoCs include more functional blocks and become more complex, its functional design and verification are much more complicated than that for CMPs.

In this paper, we present Fully-Coherent SoC (FC-SoC) model where every functional block in SoC is connected to coherent cache memory. In FC-SoC model, the communication between functional blocks is abstracted as large-scale coherent cache memory. By employing this model, hardware functional design and software programming becomes easier, and also functional block design can be isolated from communication design. This paper also presents the design methodology for FC-SoC model including a high-level synthesis method for each functional block.
Keyword (in Japanese) (See Japanese page) 
(in English) Cache coherency / chip multi-processors (CMPs) / system-on-chips (SoCs) / high-level synthesis / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 30, VLD2013-10, pp. 73-78, May 2013.
Paper # VLD2013-10 
Date of Issue 2013-05-09 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2013-10

Conference Information
Committee VLD IPSJ-SLDM  
Conference Date 2013-05-16 - 2013-05-16 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Design, etc. 
Paper Information
Registration To VLD 
Conference Code 2013-05-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) SoC System Design Methodology with Fully-Coherent Cache 
Sub Title (in English)  
Keyword(1) Cache coherency  
Keyword(2) chip multi-processors (CMPs)  
Keyword(3) system-on-chips (SoCs)  
Keyword(4) high-level synthesis  
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1st Author's Name Kodai Moritaka  
1st Author's Affiliation Nara Institute of Science and Technology (NAIST)
2nd Author's Name Hiroaki Yoshida  
2nd Author's Affiliation Fujitsu Laboratories of America, Inc. (FLA)
3rd Author's Name Mitsuru Tomono  
3rd Author's Affiliation Fujitsu Laboratories of America, Inc. (FLA)
4th Author's Name Yasuhiko Nakashima  
4th Author's Affiliation Nara Institute of Science and Technology (NAIST)
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Speaker Author-2 
Date Time 2013-05-16 16:25:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2013-10 
Volume (vol) vol.113 
Number (no) no.30 
Page pp.73-78 
#Pages 6 
Date of Issue 2013-05-09 (VLD) 

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