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Paper Abstract and Keywords
Presentation 2013-05-16 16:00
A Zero Time and Area Overhead Fault-Secure High-Level Synthesis Algorithm for RDR Architectures
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-9
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose a zero time and area overhead fault-secure high-level synthesis algorithm for RDR architectures. We duplicate some operations under a given time and area constraint and improve reliability by detecting the faults caused by soft errors. Experimental results demonstrate that our algorithm improves reliability by up to 37.73% with zero time and area overhead compared with the conventional approach.
Keyword (in Japanese) (See Japanese page) 
(in English) high-level synthesis / fault-secure / concurrent error detection / partial redundancy / RDR architecture / interconnection delays / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 30, VLD2013-9, pp. 67-72, May 2013.
Paper # VLD2013-9 
Date of Issue 2013-05-09 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2013-9

Conference Information
Committee VLD IPSJ-SLDM  
Conference Date 2013-05-16 - 2013-05-16 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Design, etc. 
Paper Information
Registration To VLD 
Conference Code 2013-05-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Zero Time and Area Overhead Fault-Secure High-Level Synthesis Algorithm for RDR Architectures 
Sub Title (in English)  
Keyword(1) high-level synthesis  
Keyword(2) fault-secure  
Keyword(3) concurrent error detection  
Keyword(4) partial redundancy  
Keyword(5) RDR architecture  
Keyword(6) interconnection delays  
Keyword(7)  
Keyword(8)  
1st Author's Name Kazushi Kawamura  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Masao Yanagisawa  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Nozomu Togawa  
3rd Author's Affiliation Waseda University (Waseda Univ.)
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Speaker Author-1 
Date Time 2013-05-16 16:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2013-9 
Volume (vol) vol.113 
Number (no) no.30 
Page pp.67-72 
#Pages 6 
Date of Issue 2013-05-09 (VLD) 

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