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Paper Abstract and Keywords
Presentation 2013-05-20 16:25
Speed-up of Dynamically Reconfigurable Processor Array
Toru Katagiri, Hideharu Amano (Keio Univ.) RECONF2013-5
Abstract (in Japanese) (See Japanese page) 
(in English) In order to achieve a high performance on the Dynamically Reconfigurable Processor Array (DRPA), it is common to increase the number of Processing Element (PE). However, since the utilization of PEs is limited depending on the parallelism on applications, increasing PE array size often does not contribute to the performance improvement. As an alternative approach, we tried a method to improve performance by speeding up PE itself rather than increasing the number of PE. First, the network of PE array is changed so as to speed up the pipelined PE. Then, the SIMD mechanism is introduced to solve data dependence produced by the pipelined PEs. As a result, the amount of hardware is reduced about 20%, the performance is improved 6.5 times, and the energy consumption is reduced by 5-28%.
Keyword (in Japanese) (See Japanese page) 
(in English) Dynamically Reconfigurable Processor / Accelerator / Spee-up / / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 52, RECONF2013-5, pp. 25-30, May 2013.
Paper # RECONF2013-5 
Date of Issue 2013-05-13 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2013-5

Conference Information
Committee RECONF  
Conference Date 2013-05-20 - 2013-05-21 
Place (in Japanese) (See Japanese page) 
Place (in English) Kochi Prefectural Culture Hall 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2013-05-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Speed-up of Dynamically Reconfigurable Processor Array 
Sub Title (in English)  
Keyword(1) Dynamically Reconfigurable Processor  
Keyword(2) Accelerator  
Keyword(3) Spee-up  
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1st Author's Name Toru Katagiri  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Hideharu Amano  
2nd Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2013-05-20 16:25:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2013-5 
Volume (vol) vol.113 
Number (no) no.52 
Page pp.25-30 
#Pages 6 
Date of Issue 2013-05-13 (RECONF) 

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