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Paper Abstract and Keywords
Presentation 2013-05-21 10:10
Design and Evaluation of FPGA-based ASIC Emulator using High-speed Serial Communication
Takashige Uda, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2013-10
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, development period of ASIC is longer becouse of the increase in circuit scale.
Verification process accounts for a lot of development time among them, so shortening the verification period is desired.
Currently, commercial FPGA-based ASIC emulator requires a cicuit partitioning when emulating a large-scale circuit.
And it's emulation frequency is remarkably reduced.
Currently, commercial FPGA-based emulator does not exist that more than emulation frequency of 10MHz or more and circuit scale of several hundreds of million ASIC gates have can be emulated.
Therefore, this paper proposes the FPGA-based ASIC emulator that has the performance of the above by using a high-speed serial communication for data communication between the FPGAs.
We discuss the feasible emulation frequency and circuit scale by the loop-back connection test of high-speed serial communication in a single FPGA .
Keyword (in Japanese) (See Japanese page) 
(in English) ASIC emulator / FPGA / High-speed Serial Communication / circuit partitioning / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 52, RECONF2013-10, pp. 49-54, May 2013.
Paper # RECONF2013-10 
Date of Issue 2013-05-13 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2013-10

Conference Information
Committee RECONF  
Conference Date 2013-05-20 - 2013-05-21 
Place (in Japanese) (See Japanese page) 
Place (in English) Kochi Prefectural Culture Hall 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2013-05-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design and Evaluation of FPGA-based ASIC Emulator using High-speed Serial Communication 
Sub Title (in English)  
Keyword(1) ASIC emulator  
Keyword(2) FPGA  
Keyword(3) High-speed Serial Communication  
Keyword(4) circuit partitioning  
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1st Author's Name Takashige Uda  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Morihiro Kuga  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ.)
3rd Author's Name Motoki Amagasaki  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ.)
4th Author's Name Masahiro Iida  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
5th Author's Name Toshinori Sueyoshi  
5th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Speaker Author-1 
Date Time 2013-05-21 10:10:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2013-10 
Volume (vol) vol.113 
Number (no) no.52 
Page pp.49-54 
#Pages 6 
Date of Issue 2013-05-13 (RECONF) 

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